参数资料
型号: MT18HTF12872G-40EC2
元件分类: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封装: DIMM-240
文件页数: 16/36页
文件大小: 672K
代理商: MT18HTF12872G-40EC2
512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
23
2003 Micron Technology. Inc.
Table 17:
Capacitance
Parameters are sampled; Vdd = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz, 0°C
TOPR +55°C, VOUT (DC) =
VDDQ/2, VOUT (peak to peak) = 0.1V
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Capacitance: CK, CK# (PLL Inputs)
CI1
2.0
3.0
pF
Input Capacitance: BA0, BA1, BA2, A0–A13, S#, RAS#, CAS#, WE#,
CKE, ODT (Registered Buffer Inputs)
CI2
2.0
3.0
pF
Input/Output Capacitance: DQ, DQS
CIO
2.5
4.0
pF
Table 18:
AC Operating Conditions
Notes: 1–5; notes appear on page 26; 0°C
TOPR +55°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC CHARACTERISTICS
-53E
-40E
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Cloc
k
Clock cycle time
CL = 4
tCK (4)
3,750
8,000
5,000
8,000
ps
CL = 3
tCK (3)
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH, tCL)
MIN (tCH,
tCL)
ps
Clock jitter
tJIT
TBD
ps
Da
ta
DQ output access time from CK/CK#
tAC
-500
+500
-600
+600
ps
Data-out high-impedance window from CK/
CK#
tHZ
tAC MAX
ps
8, 9
Data-out low-impedance window from CK/
CK#
tLZ
tAC MIN tAC MAX tAC MIN tAC MAX
ps
DQ input setup time relative to DQS
tDS
100
150
ps
DQ input hold time relative to DQS
tDH
225
275
ps
DQ input pulse width (for each input)
tDIPW
0.35
tCK
Data hold skew factor
tQHS
400
450
ps
DQ–DQS hold, DQS to first DQ to go
nonvalid, per access
tQH
tHP -tQHS
ps
Data valid output window (DVW)
tDVW
tQH -
tDQSQ
tQH -
tDQSQ
ns
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