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| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 20/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
27
2003 Micron Technology. Inc.
21. READs and WRITEs with auto precharge are
allowed to be issued before tRAS (MIN) is satisfied
since tRAS lockout feature is supported in DDR2
SDRAM.
22. VIL/VIH DDR2 overshoot/undershoot. Refer to
256Mb, 512Mb, or 1Gb DDR2 SDRAM component
data sheet for more detailed information.
23. tDAL = (nWR) + (tRP/tCK): For each of the terms
above, if not already an integer, round to the next
highest integer. tCK refers to the application clock
period; nWR refers to the tWR parameter stored in
the MR[11,10,9]. Example: For -53E at tCK = 3.75
ns with tWR programmed to four clocks. tDAL = 4
+ (15 ns/3.75 ns) clocks = 4 +(4)clocks = 8 clocks.
24. This is a minimum requirement. Minimum READ
to internal PRECHARGE timing is AL + BL/2 pro-
viding the tRTP and tRAS (MIN) have been satis-
fied. The DDR2 SDRAM will automatically delay
the internal PRECHARGE command until tRAS
(MIN) has been satisfied.
25. Operating frequency is only allowed to change
during self refresh mode or precharge power-
down mode. Anytime the operating frequency is
changed, not including jitter, the DLL is required
to be reset, followed by 200 clock cycles.
26. ODT turn-on time tAON (MIN) is when the device
leaves high impedance and ODT resistance
begins to turn on. ODT turn-on time tAON (MAX)
is when the ODT resistance is fully on. Both are
measured from tAOND.
27. ODT turn-off time tAOF (MIN) is when the device
starts to turn off ODT resistance. ODT turn off
time tAOF (MAX) is when the bus is in high
impedance. Both are measured from tAOFD.
28. This parameter has a two clock minimum require-
ment at any tCK.
29. tDELAY is calculated from tIS + tCK + tIH so that
CKE registration LOW is guaranteed prior to CK,
CK# being removed in a system RESET condition.
30. tISXR is equal to tIS and is used for CKE setup time
during self refresh exit.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
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