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参数资料
| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 2/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
10
2003 Micron Technology. Inc.
Mode Register
The mode register is used to define the specific
mode of operation of the DDR2 SDRAM. This defini-
tion includes the selection of a burst length, burst type,
CAS latency, operating mode, DLL reset, write recov-
ery, and power-down mode as shown in Figure 5. Con-
tents of the mode register can be altered by re-
executing the LOAD MODE (LM) command. If the
user chooses to modify only a subset of the MR vari-
ables, all variables (M0–M14) must be programmed
when the LOAD MODE command is issued.
The mode register is programmed via the ML com-
mand (bits M14, M13 = 0, 0) and will retain the stored
information until it is programmed again or the device
loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory array, provided it is performed
correctly.
The LOAD MODE command can only be issued (or
reissued) when all device banks are in the precharged
state. The controller must wait the specified time
tMRD before initiating any subsequent operations
such as an ACTIVE command. Violating either of these
requirements will result in unspecified operation.
Burst Length
Burst length is defined by bits M0–M3 as shown in
Figure 5. Read and write accesses to the DDR2 SDRAM
are burst-oriented, with the burst length being pro-
grammable to either four or eight. The burst length
determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE
command.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A2–A9 when the burst length is set to four
and by A3–A9 when the burst length is set to eight
(where A9 is the most significant column address bit
for a given configuration). The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst
length applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved. The burst type is
selected via bit M3 as shown in Figure 5. The ordering
of accesses within a burst is determined by the burst
length, the burst type, and the starting column address
as shown in Table 6. DDR2 SDRAM supports 4-bit
burst and 8-bit burst modes only. For 8-bit burst mode,
full interleave address ordering is supported; however,
sequential address ordering is nibble-based.
Operating Mode
The normal operating mode is selected by issuing a
LOAD MODE command with bit M7 set to zero, and all
other bits set to the desired values as shown in
Figure 5. When bit M7 is ‘1,’ no other bits of the mode
register are programmed. Programming bit M7 to ‘1’
places the DDR2 SDRAM into a test mode that is only
used by the Manufacturer and should NOT be used. No
operation or functionality is guaranteed if M7 bit is ‘1.’
Figure 5: Mode Register (MR)
Definition
NOTE:
1GB and 2GB mode registers TBD.
Burst Length
CAS# Latency BT
PD
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
97
6
5
4
3
82
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
Burst Length
Reserved
4
8
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
1
0
1
M2
0
1
0
1
Burst Type
Sequential
Interleaved
M3
CAS Latency
Reserved
2
3
4
5
Reserved
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
0
1
Mode
Normal
Test
M7
14
DLL TM
0
1
DLL Reset
No
Yes
M8
Write Recovery
Reserved
2
3
4
5
6
Reserved
M9
0
1
0
1
0
1
0
1
M10
0
1
0
1
M11
0
1
WR
MR
0
1
0
1
Mode Register
Mode Register (MR)
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
M14
0
0
1
0
1
PD Mode
Fast Exit
(Normal)
Slow Exit
(Low Power)
M12
M13
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
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