- 您现在的位置：买卖IC网 > PDF目录4024 > MT42L192M32D3LE-3 IT:A (Micron Technology Inc)IC LPDDR2 SDRAM 8GBIT 168FBGA PDF资料下载
参数资料
| 型号： | MT42L192M32D3LE-3 IT:A |
| 厂商： | Micron Technology Inc |
| 文件页数： | 6/164页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR2 SDRAM 8GBIT 168FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR2 SDRAM |
| 存储容量： | 6G（192M x 32） |
| 速度： | 333MHz |
| 接口： | 并联 |
| 电源电压： | 1.14 V ~ 1.3 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 168-VFBGA |
| 供应商设备封装： | 168-FBGA（12x12） |
| 包装： | 散装 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
List of Figures
Figure 1: 2Gb LPDDR2 Part Numbering ............................................................................................................ 3
Figure 2: Typical Self-Refresh Current vs. Temperature .................................................................................... 15
Figure 3: Single Rank, Single Channel Package Block Diagram ......................................................................... 16
Figure 4: Dual Rank, Single Channel Package Block Diagram ........................................................................... 17
Figure 5: Single Rank, Dual Channel Package Block Diagram ........................................................................... 18
Figure 6: Dual Rank, Single Channel (3 Die) Package Block Diagram ................................................................ 19
Figure 7: Dual Rank, Dual Channel Package Block Diagram ............................................................................ 20
Figure 8: Dual Rank, Dual Channel (3 Die) Package Block Diagram .................................................................. 21
Figure 9: Dual Rank, Single Channel (4 Die) Package Block Diagram ................................................................ 22
Figure 10: 134-Ball FBGA – 11mm x 11.5mm (Package Code MH) .................................................................... 23
Figure 11: 134-Ball FBGA – 11.5mm x 11.5mm (Package Code MG) .................................................................. 24
Figure 12: 168-Ball FBGA – 12mm x 12mm (Package Code KL) ......................................................................... 25
Figure 13: 168-Ball FBGA – 12mm x 12mm (Package Code KP) ......................................................................... 26
Figure 14: 168-Ball FBGA – 12mm x 12mm (Package Code LE) ......................................................................... 27
Figure 15: 216-Ball FBGA – 12mm x 12mm (Package Code KH) ........................................................................ 28
Figure 16: 216-Ball FBGA – 12mm x 12mm (Package Code KJ) ......................................................................... 29
Figure 17: 216-Ball FBGA – 12mm x 12mm (Package Code KU) ........................................................................ 30
Figure 18: 220-Ball FBGA – 14mm x 14mm (Package Code MP) ........................................................................ 31
Figure 19: 220-Ball FBGA – 14mm x 14mm (Package Code LD) ........................................................................ 32
Figure 20: 134-Ball FBGA (x16, x32) ................................................................................................................ 33
Figure 21: 168-Ball FBGA – 12mm x 12mm Single- and Dual-Die Package (SDP, DDP) ...................................... 34
Figure 22: 168-Ball FBGA – 12mm x 12mm Triple- and Quad-Die Package (3DP, QDP) ...................................... 35
Figure 23: 216-Ball 2-Channel FBGA – 12mm x 12mm ..................................................................................... 36
Figure 24: 220-Ball 2-Channel FBGA – 14mm x 14mm ..................................................................................... 37
Figure 25: Functional Block Diagram ............................................................................................................. 39
Figure 26: Voltage Ramp and Initialization Sequence ...................................................................................... 42
Figure 27: ACTIVATE Command .................................................................................................................... 54
Figure 28: t FAW Timing (8-Bank Devices) ....................................................................................................... 55
Figure 29: READ Output Timing – t DQSCK (MAX) ........................................................................................... 56
Figure 30: READ Output Timing – t DQSCK (MIN) ........................................................................................... 56
Figure 31: Burst READ – RL = 5, BL = 4, t DQSCK > t CK ..................................................................................... 57
Figure 32: Burst READ – RL = 3, BL = 8, t DQSCK < t CK ..................................................................................... 57
Figure 33: t DQSCKDL Timing ........................................................................................................................ 58
Figure 34: t DQSCKDM Timing ....................................................................................................................... 59
Figure 35: t DQSCKDS Timing ......................................................................................................................... 60
Figure 36: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 61
Figure 37: Seamless Burst READ – RL = 3, BL = 4, t CCD = 2 .............................................................................. 61
Figure 38: READ Burst Interrupt Example – RL = 3, BL = 8, t CCD = 2 ................................................................. 62
Figure 39: Data Input (WRITE) Timing ........................................................................................................... 63
Figure 40: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 63
Figure 41: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 64
Figure 42: Seamless Burst WRITE – WL = 1, BL = 4, t CCD = 2 ............................................................................ 64
Figure 43: WRITE Burst Interrupt Timing – WL = 1, BL = 8, t CCD = 2 ................................................................ 65
Figure 44: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 66
Figure 45: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 67
Figure 46: Data Mask Timing ......................................................................................................................... 67
Figure 47: Write Data Mask – Second Data Bit Masked .................................................................................... 68
Figure 48: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU( t RTP(MIN)/ t CK) = 2 ................................ 69
Figure 49: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU( t RTP(MIN)/ t CK) = 3 ................................ 70
Figure 50: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 71
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71T75802S166BGG | IC SRAM 18MBIT 166MHZ 119BGA |
| HSC31DTES | CONN EDGECARD 62POS .100 EYELET |
| HMC31DTES | CONN EDGECARD 62POS .100 EYELET |
| FMC43DRYN-S734 | CONN EDGECARD 86POS DIP .100 SLD |
| FMC43DRYH-S734 | CONN EDGECARD 86POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。