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参数资料
| 型号： | MT48V2M32LFFC |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4组同步动态RAM) |
| 中文描述： | 为512k × 32 × 4银行2.5V的内存电压（2.5V，512K采样× 32 × 4组同步动态RAM）的 |
| 文件页数： | 11/50页 |
| 文件大小： | 1058K |
| 代理商： | MT48V2M32LFFC |
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11
64Mb: x32 SDRAM, 2.5V
BatRam_25V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 2.5V
SDRAM
PRELIMINARY
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 64Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (
t
REF). Providing a distributed AUTO REFRESH
command every 15.625μs will meet the refresh require-
ment and ensure that each row is refreshed. Alterna-
tively, 4,096 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (
t
RC), once every
64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
t
RAS and may remain in self refresh mode for an indefi-
nite period beyond that.
The procedure for exiting self refresh requires a se-
quence of commands. First, CLK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for
t
XSR because time is required for the comple-
tion of any internal refresh in progress.
If, during normal operation, AUTO REFRESH cycles
are issued in bursts (as opposed to being evenly dis-
tributed), a burst of 4,096 AUTO REFRESH cycles
should be completed just prior to entering and just
after exiting the self refresh mode.
相关PDF资料 |
PDF描述 |
|---|---|
| MT48V4M32LFFC | SYNCHRONOUS DRAM |
| MT49H16M16 | THERMISTOR PTC 100OHM 110DEG RAD |
| MT49H16M16FM | REDUCED LATENCY DRAM RLDRAM |
| MT49H8M32 | THERMISTOR PTC 100OHM 120DEG RAD |
| MT49H8M32FM | REDUCED LATENCY DRAM RLDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V32M16S2FG-10 | 制造商:Micron Technology Inc 功能描述:32MX16 SSDRAM PLASTIC 2BOC 2.5V - Trays |
| MT48V32M16S2FG-8 ES | 制造商:Micron Technology Inc 功能描述:DRAM CHIP MOBILE SDRAM 512MBIT 2.5V 54FBGA - Bulk |
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