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参数资料
| 型号： | MT48V2M32LFFC |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4组同步动态RAM) |
| 中文描述： | 为512k × 32 × 4银行2.5V的内存电压（2.5V，512K采样× 32 × 4组同步动态RAM）的 |
| 文件页数： | 2/50页 |
| 文件大小： | 1058K |
| 代理商： | MT48V2M32LFFC |
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64Mb: x32 SDRAM, 2.5V
BatRam_25V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 2.5V
SDRAM
PRELIMINARY
precharge that is initiated at the end of the burst se-
quence.
The 64Mb SDRAM uses an internal pipelined archi-
tecture to achieve high-speed operation. This archi-
tecture is compatible with the 2
n
rule of prefetch archi-
tectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while ac-
cessing one of the other three banks will hide the
precharge cycles and provide seamless high-speed,
random-access operation.
The 64Mb SDRAM is designed to operate in 2.5V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 67,108,864-bits. It
is internally configured as quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
bank’s 16,777,216-bit banks is organized as 2,048 rows
by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank, A0–A10 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
相关PDF资料 |
PDF描述 |
|---|---|
| MT48V4M32LFFC | SYNCHRONOUS DRAM |
| MT49H16M16 | THERMISTOR PTC 100OHM 110DEG RAD |
| MT49H16M16FM | REDUCED LATENCY DRAM RLDRAM |
| MT49H8M32 | THERMISTOR PTC 100OHM 120DEG RAD |
| MT49H8M32FM | REDUCED LATENCY DRAM RLDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48V32M16S2FG-10 | 制造商:Micron Technology Inc 功能描述:32MX16 SSDRAM PLASTIC 2BOC 2.5V - Trays |
| MT48V32M16S2FG-8 ES | 制造商:Micron Technology Inc 功能描述:DRAM CHIP MOBILE SDRAM 512MBIT 2.5V 54FBGA - Bulk |
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