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32
64Mb: x32 SDRAM, 2.5V
BatRam_25V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 2.5V
SDRAM
PRELIMINARY
CAPACITANCE
(Notes appear on page 34)
PA RA METER
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
SY MBOL
C
I
1
C
I
2
C
IO
MIN
2.5
2.5
4.0
MA X
4.0
4.0
5.5
UNITS NOTES
pF
pF
pF
2
2
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 34) 0oC
£
T
A
£
+70oC
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
-8
-10
SYMBOL
t
AC (3)
t
AC (2)
t
AC (1)
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ (3)
t
HZ (2)
t
HZ (1)
t
LZ
t
OH
t
RAS
t
RC
t
RCD
t
REF
t
RFC
t
RP
t
RRD
t
T
t
WR
MIN
MAX
7
8
22
MIN
MAX
7
8
22
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
–
CL = 3
CL = 2
CL = 1
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
1
1
2.5
3
3
8
13
25
1
2.5
1
2.5
1
2.5
2.5
3
3
10
13
25
1
2.5
1
2.5
1
2.5
CL = 3
CL = 2
CL = 1
23
23
23
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
7
8
22
7
8
22
10
10
10
Data-out low-impedance time
Data-out hold time
ACTIVE to PRECHARGE command
AUTO REFRESH, ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time
WRITE recovery time
1
1
2.5
48
80
20
2.5
50
100
20
120,000
120,000
64
64
70
20
20
0.3
70
20
20
0.3
1.2
1.2
7
24
Auto-
Precharge
Manual
Precharge
1
t
CK +
7ns
15
1
t
CK +
5ns
15
t
WR
ns
24
Exit SELF REFRESH to ACTIVE command
t
XSR
80
100
ns
20