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参数资料
| 型号： | NAND01GR3B2CN6F |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 25000 ns, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件页数： | 17/65页 |
| 文件大小： | 1473K |
| 代理商： | NAND01GR3B2CN6F |
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Device operations
NAND01G-B2C
6.2
Cache read
The cache read operation is used to improve the read throughput by reading data using the
cache register. Since the device has only one cache register, serial data output on one page
may be executed while data from another page is read into the cache register.
A Page Read command must be issued prior to the Sequential or Random Cache Read
command in a cache read sequence. The Cache Read command can be issued only after
the read function is complete (SR6 = ‘1’).
A cache read operation consists of three steps (see Table 10: Commands):
1.
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
2.
address. If the host does not enter an address, the next sequential page is read.
3.
One bus cycle is required to issue the Cache Read Confirm command to start the
P/E/R controller.
The start address must be at the beginning of a page (column address = 00h, see Table 8
see Figure 9.
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the cache read operation has started, the status register can be read using the Read
Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the cache register is
ready to download new data.
To exit the cache read operation an Exit Cache Read command must be issued (see
Table 10).
After the device has internally read page n, the user is allowed to download data of that
page by toggling R, but the device will not trigger internally the reading of a next page.
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PDF描述 |
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| NAND01GR3B3BV1T | 128M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND01GR3B3CV6 | 128M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND01GW3B2AN6F | 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48 |
| NAND08GW3B2CZC1 | 1G X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND01GR3B3CZA1 | 128M X 8 FLASH 1.8V PROM, 35 ns, PBGA63 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GR3B2CWFD | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
| NAND01GR3B2CZA1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory |
| NAND01GR3B2CZA1E | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory |
| NAND01GR3B2CZA1F | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory |
| NAND01GR3B2CZA6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory |
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