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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 27/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
33
Intel StrataFlash Wireless Memory (L18)
7.6
AC Write Specifications
Table 10. AC Write Specifications
Num Symbol
Parameter
Min
Max Unit
s
Notes
W1
t
PHWL
RST# high recovery to WE# low
150
ns
1,2,3
W2
t
ELWL
CE# setup to WE# low
0ns
1,2,3
W3
t
WLWH
WE# write pulse width low
50
ns
1,2,4
W4
t
DVWH
Data setup to WE# high
50
ns
1,2
W5
t
AVWH
Address setup to WE# high
50
ns
W6
t
WHEH
CE# hold from WE# high
0ns
W7
t
WHDX
Data hold from WE# high
0ns
W8
t
WHAX
Address hold from WE# high
0ns
W9
t
WHWL
WE# pulse width high
20
ns
1,2,5
W10
t
VPWH
VPP setup to WE# high
200
ns
1,2,3,7
W11
t
QVVL
VPP hold from Status read
0ns
W12
t
QVBL
WP# hold from Status read
0ns
1,2,3,7
W13
t
BHWH
WP# setup to WE# high
200
ns
W14
t
WHGL
WE# high to OE# low
0ns
1,2,9
W15
t
VLWH
ADV# low to WE# high
69
ns
1,2
W16
t
WHQV
WE# high to read valid
tAVQV+35
ns
1,2,3,6,
10
Write to Asynchronous Read Specification
W18
t
WHAV
WE# high to Address valid
0ns
1,2,3,6,
10
Write to Synchronous Read Specification
W19
t
WHCH/L
WE# high to Clock valid
19
ns
1,2,3,6, 10
W20
t
WHVH
WE# high to ADV# high
19
ns
Write Specifications with Clock Active
W21
t
VHWL
ADV# high to WE# low
20
ns
1,2,3,11
W22
t
CHWL
Clock high to WE# low
20
ns
Notes:
1.
Write timing characteristics during erase suspend are the same as write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE#
or WE# high (whichever occurs first). Hence, t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHW).
6.
t
WHVH
or t
WHCH/L
must be met when transitioning from a write cycle to a synchronous burst read.
7.
VPP should be at a valid level until erase or program success is determined.
8.
This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See specs W19 and W20 for synchronous read.
9.
When doing a Read Status operation following any command that alters the Status Register, W14 is
20 ns.
10.
Add 10ns if the write operation results in a RCR or block lock status change, for the subsequent read
operation to reflect this change.
11.
These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
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