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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 39/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
44
Order Number: 313295-002US
10.0
Read Operations
The device supports two read modes: asynchronous read mode and synchronous burst
mode. Asynchronous array read mode is the default read mode after device power-up
or a reset. The Read Configuration Register (RCR) must be set before synchronous
burst operation can be performed (see Section 10.3, “Read Configuration Register
Each partition of the device can be in any of four read states: Read Array, Read
Identifier, Read Status or Read Query. To change a partition’s read state, the
appropriate read command must be written to the device (see Section 9.2, “Device
details regarding Read Status, Read ID, and CFI Query modes.
If the Read Array command is written to a partition that is performing a program or
erase operation, invalid data is read until the program or erase operation completes.
Subsequent reads produce array data. If a Program Suspend or Erase Suspend
command is issued during a program or erase operation, a subsequent Read Array
command puts the addressed partition into Read Array. The Read Array command
functions independent of VPP.
The following sections describe read-mode operations in detail.
10.1
Asynchronous Read Mode
Following a device power-up or reset, asynchronous array read is the default read
mode and all partitions are set to Read Array. However, to perform array reads after
any other device operation (e.g. write operations, reads Status, Query, ID, etc.), the
Read Array command must be issued in order to read from the flash memory array.
Each asynchronous read retrieves one data word. Asynchronous reads are permitted in
all blocks.
Note:
Asynchronous reads can only be performed when Read Configuration Register bit
RCR[15] is set (see Section 10.3, “Read Configuration Register (RCR)” on page 45).
To perform an asynchronous array or non-array read, an address is driven onto
A[MAX:16] and AD[15:0], and ADV# and CE# are asserted. WE# and RST# must
already have been deasserted. WAIT is deasserted during asynchronous read mode.
ADV# is driven high to latch the address information. CLK is not used during
asynchronous reads, and is ignored. A valid data is driven onto AD[15:0] after an initial
access delay (see Section 7.0, “AC Characteristics” on page 22).
10.2
Synchronous Burst-Mode Read
Synchronous burst mode outputs 4-, 8-, 16-, or a continuous number of contiguous
words after the device latches one address. Read Configuration register bits CR[15:0]
must be set before synchronous burst operation can be performed. (See Section 10.3,
“Read Configuration Register (RCR)” on page 45 for details). To perform a synchronous
burst read, an initial address is driven onto A[MAX:16] and AD[15:0], and ADV# and
CE# are asserted. WE# and RST# must already have been deasserted.
During synchronous array and non-array read modes, the first valid data is driven onto
AD[15:0], with respect to a valid clock edge after the asynchronous access time
(tAVQV) has been met, regardless of the latency setting. As shown in Figure 17,
setting of 4 clocks, data is driven after the third clock since the tAVQV requirement has
been met. That data continues to be available on the data bus until the first access
latency period is over, as described in Section 10.3.2, “Latency Count” on page 46. This
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