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| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 37/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
42
Order Number: 313295-002US
Table 14. Command Codes and Definitions (Sheet 1 of 2)
Mode
Code
Device Mode
Description
Read
0xFF
Read Array
Places the addressed partition in Read Array mode. Array data is output on
AD[15:0].
0x70
Read Status
Register
Places the addressed partition in Read Status Register mode. The partition enters
this mode after a program or erase command is issued. Status Register data is
output on AD[7:0].
0x90
Read Device ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads
from addresses within the partition outputs manufacturer/device codes,
Configuration Register data, Block Lock status, or Protection Register data on
AD[15:0].
0x98
Read Query
Places the addressed partition in Read Query mode. Subsequent reads from the
partition addresses output Common Flash Interface information on AD[7:0].
0x50
Clear Status
Register
The WSM can only set Status Register error bits. The Clear Status Register
command is used to clear the SR error bits.
Write
0x40
Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the WSM
executes the programming algorithm at the addressed location. During program
operations, the partition responds only to Read Status Register and Program
Suspend commands. In asynchronous mode the falling edge of OE#, or CE#
(whichever occurs first) updates and latches the Status Register contents.
However, reading the Status Register in synchronous burst mode, CE# or ADV#
must be toggled to update status data. The Read Array command must be issued
to read array data after programming has finished.
0x10
Alternate Word
Program Setup
Equivalent to the Word Program Setup command, 0x40.
0xE8
Buffered Program
Setup
First cycle of a 2-cycle command; prepares the device to receive a variable number
of bytes up to the write buffer size of 32 words. The second cycle contains the
number of bytes to be transferred.
0xD0
Buffered Program
Confirm
Issued after writing all data to the write buffer; instructs the WSM to perform its
Buffered Programming algorithm, writing the data from the write buffer to the
flash memory array.
0x80
Buffered
Enhanced
Factory
Programming
Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program
mode (Buffered EFP). The CUI then waits for the Buffered EFP Confirm command,
0xD0, that initiates the Buffered EFP algorithm. All other commands are ignored
when Buffered EFP mode begins.
0xD0
Buffered EFP
Confirm
If the previous command was Buffered EFP Setup (0x80), the CUI latches the
address and data, and prepares the device for Buffered EFP mode.
Erase
0x20
Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation.
The WSM performs the erase algorithm on the block addressed by the Erase
Confirm command. If the next command is not the Erase Confirm (0xD0)
command, the CUI sets Status Register bits SR[4] and SR[5], and places the
addressed partition in read status register mode.
0xD0
Block Erase
Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the address
and data, and the WSM erases the addressed block. During block-erase operations,
the partition responds only to Read Status Register and Erase Suspend commands.
Suspend
0xB0
Program or
Erase Suspend
This command issued to any device address initiates a suspend of the currently-
executing program or block erase operation. The Status Register indicates
successful suspend operation by setting either SR[2] (program suspended) or
SR[6] (erase suspended), along with SR[7] (ready). The Write State Machine
remains in the suspend mode regardless of control signal states (except for RST#
asserted).
0xD0
Suspend Resume This command issued to any device address resumes the suspended program or
block-erase operation.
Block Locking/
Unlocking
0x60
Lock Block Setup
First cycle of a 2-cycle command; prepares the CUI for block lock configuration
changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), or
Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5],
indicating a command sequence error.
0x01
Lock Block
If the previous command was Block Lock Setup (0x60), the addressed block is
locked.
0xD0
Unlock Block
If the previous command was Block Lock Setup (0x60), the addressed block is
unlocked. If the addressed block is in a lock-down state, the operation has no
effect.
0x2F
Lock-Down Block If the previous command was Block Lock Setup (0x60), the addressed block is
locked down.
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