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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 33/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
39
Intel StrataFlash Wireless Memory (L18)
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides
control of all in-system read, write, and erase operations of the device via the system
bus. The on-chip Write State Machine (WSM) manages all block-erase and word-
program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
9.1
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed partition. ADV#-low opens the internal
address latches. OE#-low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high. In synchronous
mode, the address is latched by the first of either the rising ADV# edge or the next
valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL).
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on
page 44 for details on the available read modes, and see Section 15.0, “Special Read
States” on page 69 for details regarding the available read states.
The Automatic Power Savings (APS) feature provides low power operation following
reads during active mode. After data is read from the memory array and the address
lines are quiescent, APS automatically places the device into standby. In APS, device
9.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. All device write operations are asynchronous, with CLK being ignored.
During a write operation, address and data are latched on the rising edge of WE# or
CE#, whichever occurs first. Table 13, “Command Bus Cycles” on page 41 shows the
bus cycle sequence for each of the supported device commands, while Table 14,
“Command Codes and Definitions” on page 42 describes each command. See Section
7.0, “AC Characteristics” on page 22 for signal-timing details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
9.1.3
Output Disable
When OE# is deasserted, device outputs AD[15:0] are disabled and placed in a high-
impedance (High-Z) state.
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