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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 7/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
15
Intel StrataFlash Wireless Memory (L18)
F-RST#
Input
FLASH RESET:
Flash-specific signal; low-true input.
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
WAIT
Output
WAIT:
Flash -and Synchronous PSRAM-specific signal; configurable true-level output.
When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output
data.
WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output
enable is low.
WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable
is high.
F-WE#
Input
FLASH WRITE ENABLE:
Flash-specific signal; low-true input.
When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched
on the rising edge of F-WE#.
R-WE#
Input
RAM WRITE ENABLE:
PSRAM- and SRAM-specific signal; low-true input.
When low, R-WE# enables Write operations for the selected memory die. Data is latched on the
rising edge of R-WE#. If device not present, treat as RFU.
2
F-WP#
Input
FLASH WRITE PROTECT:
Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
F-WP1# is dedicated to flash die #1.
F-WP2# is common to all other flash dies, if present. Otherwise it is an RFU.
P-CRE
Input
PSRAM CONTROL REGISTER ENABLE:
Synchronous PSRAM-specific signal; high-true input.
When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control
Register (P-BCR). When low, P-CRE enables normal Read or Write operations. If PSRAM not
present, treat as RFU.
3
P-MODE#
Input
PSRAM MODE#:
Asynchronous only PSRAM-specific signal; low-true input.
When low, P-MODE# enables access to the configuration register, and to enter or exit Low-Power
mode. When high, P-MODE# enables normal Read or Write operations. If PSRAM not present,
treat as RFU.
3
P[2:1]-CS#
Input
PSRAM CHIP SELECT:
PSRAM-specific signal; low-true input.
When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the
associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT
outputs are placed in a High-Z state.
P1-CS# is dedicated to PSRAM die #1. If PSRAM not present, treat as RFU.
P2-CS# is dedicated to PSRAM die #2. If PSRAM not present, treat as RFU.
S-CS1#
S-CS2
Input
SRAM CHIP SELECTS:
SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or
S-CS2 is deasserted, the SRAM die is deselected.
S-CS1# and S-CS2 are dedicated to SRAM when present. If SRAM not present, treat as RFU.
2
R-UB#
R-LB#
Input
RAM UPPER/LOWER BYTE ENABLES:
PSRAM- and SRAM-specific signals; low-true inputs.
When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read
and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. If device not
present, treat as RFU./
2
Power Signals
F-VPP
Power
FLASH PROGRAM/ERASE VOLTAGE:
Flash specific.
F-VPP supplies program or erase power to the flash die.
F[2:1]-VCC
Power
FLASH CORE POWER SUPPLY:
Flash specific.
F[2:1]-VCC supplies the core power to the flash die.
F2-VCC is recommended to be tied to F1-VCC, else it is an RFU.
Table 2.
Signal Descriptions (Sheet 2 of 3)
Symbol Type
Signal Descriptions
Notes
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