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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 63/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
66
Order Number: 313295-002US
14.2.1
Simultaneous Operation Details
The L18 device supports simultaneous read from one partition while programming or
erasing in any other partition. Certain features like the Protection Registers and CFI
Query data have special requirements with respect to simultaneous operation
capability. (Table 21 provides details on restrictions during simultaneous operations.)
14.2.2
Synchronous and Asynchronous Read-While-Write
Characteristics and Waveforms
This section describes the transitions of write operation to asynchronous read, write to
synchronous read, and write operation with clock active.
14.2.2.1
Write operation to asynchronous read transition
W18 - t
WHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when
transitioning from a write cycle (WE# going high) to perform an asynchronous read
(only address valid is required).
14.2.2.2
Write to synchronous read operation transition
W19 and W20 - t
WHCV
and t
WHVH
The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE#
High to ADV# High) is required when transitioning from a write cycle (WE# going high)
to perform a synchronous burst read. A delay from WE# going high to a valid clock
edge or ADV# going high to latch a new address must be met.
Figure 23. Operating Mode with Correct Command Sequence Example
Partition A
Data: 0x20
Partition B
Array Data
Partition A
Data: 0xD0
Addr/Data [A/D]
ADV#
CE#
WE# [W]
OE# [G]
Figure 24. Operating Mode with Illegal Command Sequence Example
Part. A
Data: 0x20
Part. B
Data: 0xFF
Part. A
Data: 0xD0
Part. A
Data: SR
Addr/Data [A/D]
ADV#
CE#
WE# [W]
OE# [G]
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