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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 61/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
64
Order Number: 313295-002US
13.2.2
Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register
command at the parameter partition’s base address plus the offset to the desired
Protection Register (see Section 9.2, “Device Commands” on page 40). Next, write the
desired Protection Register data to the same Protection Register address (see
The device programs the 64-bit and 128-bit user-programmable Protection Register
data 16 bits at a time (see Figure 38, “Protection Register Programming Flowchart” on
page 86). Issuing the Program Protection Register command outside of the Protection
Register’s address space causes a program error (SR[4] set). Attempting to program a
locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1]
set).
Note:
If a program or erase operation occurs when programming a Protection Register,
certain restrictions may apply. See Table 21, “Simultaneous Operation Restrictions” on
page 68 for details.
13.2.3
Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the
Lock Register. To lock a Protection Register, program the corresponding bit in the Lock
Register by issuing the Program Lock Register command, followed by the desired Lock
Register data (see Section 9.2, “Device Commands” on page 40). The physical
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the lock registers (see Table 23, “Device
Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-
programmed 64-bit region of the first 128-bit Protection Register containing the unique
identification number of the device. Bit 1 of Lock Register 0 can be programmed by the
user to lock the user-programmable, 64-bit region of the first 128-bit Protection
Register. The other bits in Lock Register 0 are not used.
Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers.
Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit
Protection Registers. Programming a bit in Lock Register 1 locks the corresponding
128-bit Protection Register.
Caution:
After being locked, the Protection Registers cannot be unlocked.
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