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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 44/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
49
Intel StrataFlash Wireless Memory (L18)
NOTE:
Active: WAIT is asserted until data becomes valid, then de-asserts. WAIT is asserted during the initial
access (latency) and at the end of the burst cycle with OE# low.
10.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains valid on AD[15:0] for one or two clock cycles. This period of time is called the
“
data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see Figure 18). The processor’s data setup
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks.
A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 54 MHz, the clock period is 18.5 ns. Assuming
tCHQV = 14ns and tDATA = 4ns. Applying these values to the formula above:
14 ns + 4 ns ≤ 18.5 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock.
If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods
must be used.
OE# = VIH
OE# = VIL
De-asserted
Active
Synchronous Array and
Non-array Reads
Active
All Asynchronous Read and
all Write
De-asserted
Table 18. WAIT Summary Table
CONDITION
WAIT
Figure 18. Data Hold Timing
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
CLK [C]
AD[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
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