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参数资料
| 型号： | PF38F40L0YUQ0 |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封装： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件页数： | 31/99页 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
37
Intel StrataFlash Wireless Memory (L18)
8.3
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power
supply current considerations are as follows:
1. Standby current levels
2. Active current levels
3. Transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
decoupling capacitor selection suppress transient voltage peaks.
Figure 15. Reset Operation Waveforms
Table 12. Reset Specifications
Num Symbol
Parameter
Min
Max
Unit
Notes
P1
tPLPH
RST# pulse width low
100
ns
1,2,3,4
P2
t
PLRH
RST# low to device reset during erase
25
s
1,3,4,7
RST# low to device reset during program
25
1,3,4,7
P3
tVCCPH
VCC Power valid to RST# deassertion (high)
60
1,4,5,6
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if t
PLPH
is <t
PLPH
MIN, but this is not guaranteed.
3.
Not applicable if RST# is tied to Vcc.
4.
Sampled, but not 100% tested.
5.
If RST# is tied to the V
CC
supply, device will not be ready until t
VCCPH
after V
CC
>= V
CC
min.
6.
If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed
VCC until VCC >= VCC(min).
7.
Reset completes within t
PLPH
if RST# is asserted while no erase or program operation is executing.
(A) Reset during
read mode
(B) Reset during
program or block erase
P1
≤ P2
(C) Reset during
program or block erase
P1
≥ P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1
R5
P2
P3
P2
R5
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