参数资料
型号: PF38F40L0YUQ0
厂商: NUMONYX
元件分类: PROM
英文描述: 16M X 16 FLASH 1.8V PROM, PBGA88
封装: 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件页数: 92/99页
文件大小: 1419K
代理商: PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
92
Order Number: 313295-002US
Table 32. Protection Register Information
Offset
(1)
Length
Description
Hex
P= 10Ah
(Optional flash features and commands)
Add.
Code
Value
(P+E)h
1
118:
--02
2
(P+F)h
4
Protection Field 1: Protection Description
119:
--80
80h
(P+10)h
This field describes user-available One Time Programmable
11A:
--00
00h
(P+11)h
(OTP) Protection register bytes. Some are pre-programmed
11B:
--03
8 byte
(P+12)h
11C:
--03
8 byte
(P+13)h
10
Protection Field 2: Protection Description
11D:
--89
89h
(P+14)h
11E:
--00
00h
(P+15)h
11F:
--00
00h
(P+16)h
120:
--00
00h
(P+17)h
121:
--00
0
(P+18)h
bits 40–47 = “n”
∴ n = factory pgm'd groups (high byte)
122:
--00
0
(P+19)h
123:
--00
0
(P+1A)h
124:
--10
16
(P+1B)h
125:
--00
0
(P+1C)h
126:
--04
16
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2
n = factory pre-programmed bytes
bits 24–31 = “n” such that 2
n = user programmable bytes
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n”
∴ n = factory pgm'd groups (low byte)
bits 48–55 = “n” \ 2
n = user programmable bytes/group
bits 56–63 = “n”
∴ n = user pgm'd groups (low byte)
bits 64–71 = “n”
∴ n = user pgm'd groups (high byte)
bits 72–79 = “n”
∴ 2
n = user programmable bytes/group
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