参数资料
型号: PF38F40L0YUQ0
厂商: NUMONYX
元件分类: PROM
英文描述: 16M X 16 FLASH 1.8V PROM, PBGA88
封装: 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件页数: 30/99页
文件大小: 1419K
代理商: PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
36
Order Number: 313295-002US
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected
together. If VCCQ and/or VPP are not connected to the VCC supply, then VCC should
attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before
supply voltage equals VCCMIN.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
8.2
Reset
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active-low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
System designers should guard against spurious writes when VCC voltages are above
VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting
either signal inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because
alteration of memory contents can only occur after successful completion of a two-step
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