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参数资料
| 型号： | PM8621-BIAP |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | NSE-8G⑩ Standard Product Data Sheet Preliminary |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA480 |
| 封装： | 35 X 35 MM, 1.47 MM HEIGHT, UBGA-480 |
| 文件页数： | 50/184页 |
| 文件大小： | 1122K |
| 代理商： | PM8621-BIAP |
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NSE-8G Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
49
9.3.6
SBI336S Multiframe Alignment
SBI336S multiframe alignment is communicated across the link by controlling the frequency of
the C1FP character. The most frequent transmission of the C1FP character is every four SBI336S
frame times. This is the SBI336S multiframe and is used when there are no synchronous
tributaries requiring signalling multiframe alignment on the SBI336S bus. When there are
synchronous tributaries on the SBI336S bus the C1FP character is transmitted every 48 frame
times. This is the CAS signaling multiframe and is the lowest common multiple of the 24 frame
T1 multiframe and the 16 frame E1 multiframe.
The SBI336S multiframe and signaling multiframe alignment is based a free running multiframe
counter that is reset with each C1FP character received. Under normal operating conditions each
received C1FP character will coincide with the free running multiframe counter. SBI336S
multiframe alignment is always required, SBI336S signaling multiframe alignment is optional
and only required when synchronous tributaries are supported with DS0 level switching.
9.4
DS0 Cross Bar switch (DCB)
Each of 12 R8TD blocks provides an eight-bit data signal on each 77.76 MHz clock edge. These
signals are the STS-12 frame aligned ingress octets. Likewise, each of 12 egress T8TE blocks
expects to receive a STS-12 frame aligned signal on each clock edge. The DS0 Cross Bar switch
(DCB) connects these inputs to these outputs.
The DCB constitutes a Space switch that connects each output to some input during each clock
period in the STS-12 frame structure. The STS-12 frame structure consists of 12*9*90 = 9720
octets (of overheads and payload). Being a DS0 granularity space switch, the DCB must provide
separate switch settings for each of these 9720 octet times.
These 9720 switch settings are stored in an on-chip SRAM. Each of twelve egress ports must be
told which of each of twelve
ingress ports it should read during each of the 9720 clock periods.
Five bits are required to specify which ingress port should be read by each output. Thus, we
require 9720 words of five bits each for twelve
egress ports. Thus each clock period requires 12
*5 = 60 bits. To support controlled switchover from one set of switch settings to another, we
require two banks of 9720 words each. The aggregate memory requirement is 2 X 9720 X 60b =
1,166,400b of SRAM. Table 4 illustrates the mapping of this memory. Each control page in the
table is a vector of 60 bits containing five bits (specifying the source port) for each of 12 egress
ports. One page will be on-line translating ports in the core switch while the other is offline for
CPU update. When the new configuration is ready, and the appropriate system synchronized
frame boundary arrives, the pages will be swapped.
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