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参数资料
| 型号： | PM8621-BIAP |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | NSE-8G⑩ Standard Product Data Sheet Preliminary |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA480 |
| 封装： | 35 X 35 MM, 1.47 MM HEIGHT, UBGA-480 |
| 文件页数： | 52/184页 |
| 文件大小： | 1122K |
| 代理商： | PM8621-BIAP |
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NSE-8G Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
51
9.9
In-band Link Controller (ILC)
In order to permit centralized control of distributed NSE/SBS fabrics from the NSE-8G
microprocessor interface (for applications in which NSEs are located on fabric cards, and SBSs
are located on multiple line cards), an in-band signaling channel is provided between the NSE-8G
and the SBS over the Serial SBI336S interface. Each NSE-8G can control up to 12 SBSs that are
attached by the LVDS links. The NSE-SBS in-band channel is full duplex, but the NSE-8G has
active control of the link.
The in-band channel is carried in the first 36 columns of four rows of the SBI structure, rows 3, 6,
7 and 8. The overall in-band channel capacity is thus 36*4*64 kb/s = 9.216 Mbit/s. Each 36 bytes
per row allocated to the in-band signaling channel is its own in-band message between the end
points. Four bytes of each 36 byte inband message are reserved for end-to-end control
information and error protection, leaving 8.192 Mbit/s available for data transfer between the end
points.
The data transferred between the end points has no fixed format, effectively providing a clear
channel for packet transfer between the attached microprocessors at each of the LVDS link
terminating devices. The user is able to send and receive any packet up to 32 bytes in length. The
last two reserved bytes of the 36 byte in-band message is a CRC-16 which detects errors in the
message. This block provides a microprocessor interface to the in-band signaling channel.
This in-band channel is expected to be used almost entirely to carry out switching control changes
in the SBSs. To configure a DS0 in an SBS device most often requires a local microprocessor to
write to one memory location consisting of a 16-bit address and a 16-bit data. Using this as a
baseline and assuming an efficient use of the in-band channel bandwidth, we can set a maximum
of (32bytes/row * 4 rows/frame * 8000 frames/sec / 4 bytes/write) 256,000 DS0 configurations
per second.
Considering that configuring a T1 when switching DS0s requires 27 DS0 writes, indicates that
the in-band signaling channel bandwidth sets maximum limit of over 9000 T1 configurations per
second. In real life these limits will not be achieved but this shows that the in-band link should
not be the bottleneck. In TelecomBus mode, this same configuration will require only three writes
per T1 link. Another more efficient communication scheme could be used to increase this
performance.
In N+1 protected architectures, it is likely that full configuration of a port card will be necessary
during the switchover. This would require the entire connection memory be reconfigured.
Assuming connections for overhead bytes are also reconfigured, the fastest that a complete
reconfiguration can take place is 9720 register writes for each of the two configuration pages in
the SBS. This equates to (2 * 9720 writes * 4 bytes/write / (32 bytes/row * 4 rows/frame * 8000
frames/second)) 76 milliseconds. It is also possible that the spare card could hold all the
connection configurations for all the port cards it is protecting locally, for even faster switch over.
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