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| 型号： | RC28F160C3BD70 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 70 ns, PBGA64 |
| 封装： | BGA-64 |
| 文件页数： | 39/72页 |
| 文件大小： | 1083K |
| 代理商： | RC28F160C3BD70 |
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Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
44
Order Number: 290645, Revision: 023
When VPP is connected to a 12 V power supply, the device draws program and erase current
directly from the VPP pin. This eliminates the need for an external switching transistor to control
various usage models.
The 12 V VPP mode enhances programming performance during the short period of time typically
found in manufacturing processes; however, it is not intended for extended use. You cna apply
12 V to VPP during Program and Erase operations for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80
hours maximum. Stressing the device beyond these limits may cause permanent damage.
10.2.2
Suspending and Resuming Program
The Program Suspend command halts an in-progress program operation so that data can be read
from other locations of memory. Once the programming process starts, issuing the Program
Suspend command to the CUI requests that the WSM suspend the program sequence at
predetermined points in the program algorithm. The device continues to output Status Register data
after the Program Suspend command is issued. Polling SR[7] and SR[2] will determine when the
program operation has been suspended (both will be set to “1”). The program-suspend latency is
specified with tWHRH1/tEHRH1.
A Read-Array command can now be issued to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended are Read Status
Register, Read Identifier, CFI Query, and Program Resume.
After the Program Resume command is issued to the flash memory, the WSM will continue with
the programming process and SR[2] and SR[7] will automatically be cleared. The device
automatically outputs Status Register data when read (see Figure 18, “Program Suspend / Resume
same VPP level used for program while in program-suspend mode. RP# must also remain at VIH.
10.3
Erase Mode
To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the Status Register indicates that erasure is complete, check the erase-status bit to verify that
the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the Status
Register will be set to a “1,” indicating an erase failure. If VPP is not within acceptable limits after
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR[5] of the Status Register is set to indicate an erase error, and SR[3] is set to a “1” to identify that
VPP supply voltage is not within acceptable limits.
After an Erase operation, clear the Status Register (0x50) before attempting the next operation.
Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status-
register reads, Intel recommends that you place the flash in read-array mode after the erase is
complete.
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