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参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 13/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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20
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
The on-chip PLL consists of; a phase detector, which
compares the phase relationship between the VCO
output and the CSU_REFCLK input, a loop filter, which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by this
voltage.
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. A single external clean-up capacitor is
utilized as part of the loop filter. The loop filter’s corner
frequency is optimized to minimize output phase jitter.
Loop Timing
In Serial Loop Timing mode (SLPTIME), the clock syn-
thesizer PLL of the S19237 is bypassed, and the timing
of the entire transmitter section is controlled by the
Receive Serial Clock (RSCLK [Internal]). This mode is
entered by setting the SLPTIME input to a logic high. In
this mode the CSU_REFCLKP/N input is not used for
data transmission, and the REFSEL inputs are ignored
for all transmit functions. TX_155MCK and PCLK are
derived from the internal RSCLK. The XVCO select
input must be programmed to logic low in the SLP-
TIME mode. The external VCO can never be used in
the SLPTIME mode. When operating the S19237 in
SLPTIME mode, the TX_155MCK output should not be
used as the backup reference clock (CRU_REFCLK)
for the clock recovery unit.
In Reference Loop Timing mode (RLPTIME), the Paral-
lel Clock (POCLK) from the receiver is used as the
reference clock to the transmitter. In this mode, the
CSU_REFCLKP/N input is not used. The TX_155MCK
is generated from the POCLK in this operating mode.
When operating the S19237 in RLPTIME mode, the
TX_155MCK output should not be used as the backup
reference clock (CRU_REFCLK) for the clock recovery
unit. When performing loopback testing (DLEB), the
S19237 must not be in RLPTIME mode.
The XVCO input must be programmed to logic high in
the RLPTIME mode. The external VCO is always used
in the RLPTIME mode. The internal POCLK will
always be fed into the external tracking filter (filter and
VCO) for cleanup in the RLPTIME mode. The output of
the external VCO (which is fed into the CSU_IN input)
will be used as the reference clock for the CSU.
The XVCO mode is must be programmed to logic low
in SLPTIME and programmed to logic high in RLP-
TIME mode. The SLPTIME mode takes precedence
over the RLPTIME mode. The SLPTIME mode must
be held inactive for the RLPTIME mode to be active.
Line Loopback
The line loopback circuitry selects the source of the
data that is output on the TSD. When the Line Loop-
back Enable (LLEB) input is inactive (high), it selects
data and clock from the parallel-to-serial converter
block. When LLEB is active (low), it forces the output
data multiplexer to select the data from the RSD (inter-
nal) input, and a receive-to-transmit loopback can be
established at the serial data rate. The parallel data
outputs POUT[15:0] and parallel output clock POCLK
are accessible in the LLEB mode.
Timing Generator
The timing generator function, shown in the block dia-
Diagram, provides a 16-bit parallel rate clock output.
The PCLK output is a 16-bit parallel clock. For
STS-192, the PCLK frequency is 622.08 MHz. PCLK
is intended for use as a 16-bit parallel speed clock for
upstream multiplexing and overhead processing cir-
cuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S19237 device.
In the parallel-to-serial conversion process, the incom-
ing data is passed from the PICLK clock timing domain
to the internally generated PCLK clock timing domain.
The timing generator also produces a feedback refer-
ence clock to the clock synthesizer. A counter divides
the synthesized clock down to the same frequency as
the Transmit Reference Clock (CSU_REFCLK). The
PLL in the clock synthesizer maintains the stability of
the synthesized clock by comparing the phase of the
feedback clock with that of the CSU_REFCLK. The
modulus of the counter is a function of the reference
clock frequency.
FIFO
A FIFO is added to decouple the internal and external
parallel clocks. The internally generated divide-by-16
clock (PCLK) is used to clock out data from the FIFO.
PHINIT and TX_LOCKDET are used to center or reset
the FIFO. The PHINIT and TX_LOCKDET signals will
center the FIFO once they have been asserted (high).
(See Figure 23, FIFO Initialization). This is in order to
ensure that PICLK is stable. This scheme allows the
user to have an infinite PCLK-to-PICLK delay through
the ASIC. Once the FIFO is centered, the PCLK-to-
PICLK delay can have a maximum drift as specified in
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相关代理商/技术参数 |
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|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
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