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参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 2/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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10
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
External Voltage Controlled Oscillator (XVCO) –
MDIO Register
The XVCO is the active high control input that selects
CSU_IN as the reference clock for the CSU block.
When active, the CSU_IN (output of the external VCO)
input is used as the reference clock for the CSU for
improved jitter generation. When inactive and in the
normal mode, the CSU_REFCLK is directly used as
the reference clock for the CSU block. This input is
only accessible through the MDIO bus register.
Clock Synthesizer Input (CSU_INP/N) – External
Pin
The clock synthesizer input is the differential REFCLK
CML input to the internal CSU. This input is typically
driven from an external VCO, which is controlled by an
external loop filter and the internal phase detector out-
put (PD_UP, PD_DWN). CSU_IN will be used as the
reference clock for the CSU block when XVCO control
input is active. The S19237 may have improved jitter
generation when CSU_IN is used as the reference
clock for the CSU blo ck ra the r th an the
CSU_REFCLK. See Figures 18 and 19 for details.
This input is internally biased and terminated and must
be AC coupled.
Reference Select (REFSEL) – MDIO Register
The Reference Select (REFSEL) input selects
between a 155.52 MHz or 622.08 MHz (or equivalent
FEC/10 Gigabit Ethernet rate) reference clock
(CSU_REFCLK). See Table 1, Reference Frequency
Case 1. XVCO Select Input is Inactive – In this
mode, the external VCO is bypassed. The output of
the internal phase detector (PD block shown in
Figure 5) is not used. The REFSEL input selects either
the 155.52 MHz or 622.08 MHz reference frequency
(CSU_REFCLK input). Accordingly, the CSU operates
in the 155.52 MHz or 622.08 MHz CSU_REFCLK
mode. Case 2. XVCO Select Input is Active – In this
mode, the external VCO is used. The output of the
phase detector block (PD_UP/DWN) is fed into the
external filter/VCO. The output of the external VCO is
fed into the CSU_IN input. Since the output of the
external VCO is always 622.08 MHz, the REFSEL
forces the CSU to operate in the 622.08 MHz
CSU_REFCLK mode.
REFSEL input should be programmed to logic low
when CSU_REFCLK = 155.52 MHz. This enables the
CSU_IN divide by four (622.08 MHz Divide by four =
155.52 MHz) to go into one of the Phase Detector
(PD) inputs. The 155.52 MHz CSU_REFCLK directly
goes into the second PD input. REFSEL should be
programmed to logic high when CSU_REFCLK =
622 .08 MHz. This wo uld en able t h e CSU_IN
(622.08 MHz output of the external VCO) directly into
one of the Phase Detector (PD) inputs (CSU_IN
Divide by four is not selected when REFSEL is high).
The 622.08 MHz CSU_REFCLK goes directly into
the second Phase Detector (PD) input. See Table 2,
This input is only accessible through the MDIO bus
register.
TX Loop Filter (TXCAP1, TXCAP2) – External Pin
The transmit clock synthesizer unit external loop filter
capacitor and resistors are connected to these pins.
These devices should be surrounded by a ground
shield. The component values are as stated in
Table 33, Transmit and Receive External Loop Filter
Components.
Phase Initialization (PHINIT) – MDIO Register
The active high Phase Initialization (PHINIT) input is
an asynchronous input that initializes the internal
phase adjust circuit for the transmitter FIFO. When
active, this input will align the PICLK and the inter-
nally generated PCLK. When AUTO_FIFO_INIT is
not enabled, PHINIT must be asserted if the PHERR
signal is active which indicates potential internal
setup/hold timing violations. See Figure 23, FIFO Ini-
tialization. This input is only accessible through the
MDIO bus register.
Table 2. Reference Frequency with External VCO Selected
XVCO
REFSEL
CSU_REFCLK
CSU_IN Frequency
CSU Mode
0
155.52 MHz
X
155.52 MHz
0
1
622.08 MHz
X
622.08 MHz
1
0
155.52 MHz
622.08 MHz
1
622.08 MHz
The BOLD CELLS denote the default state
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
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