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参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 8/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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16
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
RECEIVE OUTPUT PIN DESCRIPTION
Parallel Output Clock (POCLKP/N) – External Pin
The LVDS Parallel Output Clock (POCLKP/N) output
is an internally regenerated clock which is used to
transfer demultiplexed data from an internal holding
register to the output register, which drives the parallel
output data bus POUTP/N [15:0]. This clock is syn-
chronized with the parallel output data. According to
OIF99.102.5, section 9.0, the clock edges should align
to the data edges in order to simplify the driver macro
design for the SERDES and framers. The rising edge
of the POCLKP/N is instead centered with the output
data valid window (POUTP/N[15:0]). This simplifies
the board design, as delaying the clock on the board is
not required.
Parallel Output Data (POUTP/N[15:0]) –
External Pin
The Parallel Output Data (POUTP/N[15:0]) LVDS out-
puts are re-timed data that are output from the
demultiplexer at a rate of 622.08 Mbps (or equivalent
FEC/10 Gigabit Ethernet rate). Bit 15 is the most sig-
nificant bit and is the first received bit. The data is re-
timed and synchronized to the Parallel Output Clock
(POCLKP/N). This bus is typically connected to a
framer, mapper or digital wrapper (e.g. AMCC's KHA-
TANGA, GANGES or HUDSON).
Receive Lock Detect (RX_LOCKDET) – MDIO Reg-
ister and External Pin
Active high LVCMOS Lock Detect (RX_LOCKDET)
signal indicates a valid incoming data stream. When
inactive (low), it indicates that the incoming data
stream has failed the frequency test as dictated by the
PLL or that LCKREFN has been asserted low or
SDLVCMOS has been de-asserted. This test is used
to determine if the serial input data is valid. When
RX_LOCKDET is active, the PLL is locked to the data
stream. This output can be accessed through the
MDIO bus register and external LVCMOS pin.
Recovered 622.08 MHz Clock (RX_622MCKP/N) –
External Pin
The LVDS 622.08 MHz Clock (or equivalent FEC/10
Gigabit Ethernet rate) (RX_622MCKP/N) is the clock
which is recovered from the input data stream. During
loss-of-signal conditions, or when LCKREFN has been
asserted, this output clock is derived from the Refer-
ence Clock Input (CRU_REFCLKP/N). This clock may
be used to drive the reference clock input of the trans-
mit side (CSU_REFCLKP/N) of the S19237.
Receive Built-In Self Test Error (RX_BIST_ERR) –
MDIO Register
The active high receive Built-In Self Test Error
(RX_BIST_ERR) signal indicates a bit error in the
receive built-in self test loop. After the receive checker
is initialized, it will compare the parallel data input with
the calculated pattern. If the parallel data input does
not match the calculated pattern, the RX_BIST_ERR
flag will be set active. The RX_BIST_ERR flag can be
clea re d b y asse rtin g RX_ B IST_ CLR in th e
RX_BIST_EN mode or by resetting (RSTB) the
S19237. The RX_BIST_ERR can also be cleared with
a rising edge of RX_BIST_EN. This output is only
accessible through the MDIO bus register.
COMMON INPUT PIN DESCRIPTION
Reset (RSTB) – External Pin
This active low LVCMOS Reset (RSTB) input asyn-
chronously resets the device. All clocks, including
PCLK, are disabled during reset. For normal system
operation, VDD_1.8V should be connected to RSTB input.
This input should be active for 100 ns to accurately
reset the device. This input can be accessed through
the external LVCMOS input pin.
Diagnostic Loopback Enable (DLEB) –
MDIO Register
The DLEB is an active low input that selects the diag-
nostic loopback mode. In this mode, the Transmitter
Data (TSD) is routed internally from the transmitter to
the receiver. When DLEB mode is enabled, the
received parallel data from the framer/mapper transmit
path is routed back to the receive parallel data path of
the framer/mapper. This mode allows the digital side of
the node to be isolated from the rest of the network.
The received serial data, SERDATIP/N, will not be
passed on to the framer/mapper. The network, how-
ever, will receive the aligned high-speed data TSD,
when DLEB mode is active. This input is only accessi-
ble through the MDIO bus register.
Line Loopback Enable (LLEB) – MDIO Register
This active low input selects line loopback mode. In
this mode, the internal receiver data (RSD[15:0]) is
routed internally from the receiver to the transmitter.
When the LLEB is enabled, the parallel output data
RSD[15:0] (internal signal) is routed to the parallel
input data path PIN[15:0]. The parallel data outputs
POUT[15:0] and parallel output clock POCLK are
accessible in the LLEB mode.
Case 1. XVCO select input is active. When LLEB
and XVCO inputs are active, the internal POCLK acts
as the timing source for the CSU block. In this case,
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
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