- 您现在的位置：买卖IC网 > PDF目录192292 > S19237PB13 (APPLIEDMICRO INC) TRANSCEIVER, PBGA255 PDF资料下载
参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 19/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
26
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
SONET Jitter Generation
The following jitter generation requirement applies to
STS-192 interfaces as defined in GR-253-CORE.
According to GR-253-CORE, jitter generation shall
not exceed 0.10 UIPP for STS-192 interfaces when
measured using a bandpass measurement filter
with a high-pass cutoff frequency of 50 kHz and a
low-pass cutoff frequency of at least B3 = 80 MHz.
Note that for SONET rates up to STS-48, the cur-
rent jitter generation requirement in GR-253-CORE
states that the generated jitter must be less than
0.01 UI rms and 0.10 UIPP. At the STS-192 rate,
the measurement of RMS phase variations with
less than 0.01 UI granularity (1 picosecond) may
not be feasible. Therefore, this requirement speci-
fies the jitter generation only in terms of 0.10 UIPP.
The S19237 meets the Telecordia Jitter Generation
Specification by having a worst-case jitter generation
of 3 mUIRMS in the normal mode of operation.
10 Gigabit Ethernet Jitter Tolerance
The following 10 Gigabit Ethernet jitter tolerance
requirement applies to 10GBASE-ER as defined in
IEEE Draft P802.3ae/D4.0. This total jitter is com-
posed of three components: deterministic jitter;
random jitter; and an additional sinusoidal jitter.
The three fundamental components of Jitter Tolerance
testing are:
Input Jitter (Dj and Rj)
Sinusoidal Jitter
Test Pattern (Test patterns are different for
10GBASE-R and 10GBASE-W)
Input Jitter (amount of Dj and Rj)
Dj: 0.35 UI pk-pk
Rj: 0.015 UI rms
The random jitter (RJ) component of the input signal
has uniform spectral content over the measurement
frequency range of at least 1 MHz to 1 GHz per sec-
tion 52.8.2.1 of IEEE Draft P802.3ae/D4.0. Input
Signal must pass the bathtub curves between BERs of
The input jitter used to test receiver jitter tolerance is
specified by the receiver input jitter mask defined in by
the following equations (W and sigma are Dj and Rj
respectively):
Where:
Sinusoidal Jitter
The Sj applied for tolerance testing is defined by the
52.8.2.2 of IEEE Draft P802.3ae/D4.0). The Loop
Bandwidth (LB) for S19237 is approximately 8 MHz.
Test Pattern
Test pattern is chosen per IEEE Draft P802.3ae/D4.0
Section 52.8.2. The test pattern is a static pattern and
can be loaded into a BERT. IEEE Draft P802.3ae/D4.0
specifies two pseudo-random test patterns for
10GBASE-ER testing. One pattern represents typical
scrambled data while the other represents a less typi-
cal pattern which could happen by chance and is
thought to be more demanding of the transmission
process including the clock recovery sub-system. Both
patterns are balanced over their length of 33792 bits.
Test pattern is constructed from 4 Segments
1 segment is constructed with 128 Blocks
1 block is 2 Sync Bits and 64 Payload Bits
Pay load bits are generated with the scrambler
shown in Figure 10.
Data input is set to 1 or 0.
Log
10 BER
() AB t 0.5W
–
σ
--------------------
2
–
≥
Log
10 BER
() AB 1 t
–0.5W
–
σ
-----------------------------
2
–
≥
A
1.75 B
Log10 e
()
2
------------------------
0.217
=
,
–
=
相关PDF资料 |
PDF描述 |
|---|---|
| S1950E-FREQ-OUT25 | CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 125 MHz, ACMOS OUTPUT |
| S1F78100Y2A0 | 6 V FIXED POSITIVE REGULATOR, PSSO3 |
| S1F78100Y2B0 | 5 V FIXED POSITIVE REGULATOR, PSSO3 |
| S1F78100Y2C0 | 3.2 V FIXED POSITIVE REGULATOR, PSSO3 |
| S1F78100Y2F0 | 2.2 V FIXED POSITIVE REGULATOR, PSSO3 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
发布紧急采购，3分钟左右您将得到回复。