44
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
Jgen jitter generation
TSD (RLPTIME Mode)
2
3
mUI
(RMS)
In-lock, integrated phase
noise of the external VCO
should be -54dBc or better
within 50 kHz to 80 MHz B.W.
10 Gigabit Ethernet Jitter Specifications
10 Gigabit Ethernet Jtol Jitter Tolerance
(SERDATIP/N)
0.015
UI
(RMS)
Random Jitter. Equalization
turned on and optimized
0.35
UI (p-p)
Deterministic Jitter. Equaliza-
tion turned on and optimized
UI (p-p)
40 KHz < f < 10 LB
(Sinusoidal). Equalization
turned on and optimized
XFP (XFI) Jitter Specifications
Total Jitter (Receiver)
0.65
UI (p-p)
Equalization turned on and
optimized
Total Non-DDJ Jitter (Receiver)
0.45
UI (p-p)
Equalization turned on and
optimized
Sinusoidal Jitter Tolerance (Receiver)
See Figures
16 and
17 for the Telecom and Datacom mask
Eye Mask X1 (Receiver)
0.325
UI
See Figure
15, X1=0.225 if
total non DDJ is measured
Eye Mask Y1 (Receiver)
55
mV
Eye Mask Y2 (Receiver)
525
mV
Deterministic Jitter TSD (Transmitter)
0.15
UI (p-p)
Normal Mode.
Total Jitter TSD (Transmitter)
0.30
UI (p-p)
Normal Mode.
Eye Mask X1 (Transmitter)
0.15
UI
Eye Mask X2 (Transmitter)
0.4
UI
Eye Mask Y1 (Transmitter)
180
mV
Eye Mask Y2 (Transmitter)
385
mV
Jgen jitter generation
TSD (Normal Mode with 622.08 MHz
CSU_REFCLK)
2
2.5
mUI
(RMS)
In-lock, 50kHz to 8MHz B.W.
From 9.9 GHz to 10.709 GHz
Jgen jitter generation
TSD (Normal Mode with 155.52 MHz
CSU_REFCLK)
4
4.5
mUI
(RMS)
In-lock, 50kHz to 8MHz B.W.
From 9.9 GHz to 10.709 GHz
Reference Clock Specifications
Receive Reference clock frequency toler-
ance (CRU_REFCLK)
-100
+100
ppm
± 20 ppm is required to meet
SONET output frequency
specification.
Table 22. Performance Specifications (Continued)
Parameter
Min
Typ
Max
Units
Conditions