- 您现在的位置：买卖IC网 > PDF目录192292 > S19237PB13 (APPLIEDMICRO INC) TRANSCEIVER, PBGA255 PDF资料下载
参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 14/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
21
Data Sheet
The FIFO shown in Figure 5, Transceiver Functional
Block Diagram, is comprised of two sets of registers.
The 622.08 MHz (or equivalent FEC/10 Gigabit Ether-
net rate) clocks in the data from the PINP/N[15:0] bus
to the first register of the FIFO. A second register is a
parallel loadable shift register which takes its parallel
input from the first register.
An internally generated PCLK clock, which is phase
aligned to the transmit serial clock, activates the paral-
lel data transfer between registers. This 16-bit data is
fed into the parallel-to-serial converter.
FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1.
During power up, once the PLL has locked to the
reference clock provided on the CSU_REFCLK
pins, the TX_LOCKDET will go active and initialize
the FIFO.
2.
When RSTB goes active, the entire transmitter is
reset. This causes the PLL to go out of lock, thus
the TX_LOCKDET goes inactive. When the PLL
reacquires the lock, the TX_LOCKDET goes
active and initializes the FIFO. Note that PCLK is
held in reset when RSTB is active.
3.
When AUTO_FIFO_INIT is not enabled, the user
can also initialize the FIFO by raising PHINIT
input.
During normal running operation, the incoming data is
passed from the PICLK timing domain to the internally
generated divide-by-16 clock timing domain. Although
the frequency of PICLK and the internally generated
clock (PCLK) are the same, their phase relationship is
arbitrary. To prevent errors caused by short setup or
hold times between the two timing domains, the FIFO
circuitry monitors the phase relationship between
PICLK and the internally generated clock. When a
potential setup or hold time violation is detected,
Phase Error (PHERR) goes high. If the condition per-
sist s,
PHERR
wil l
remain
high.
When
AUTO_FIFO_INIT is not enabled, if PHERR conditions
occur, PHINIT should be activated to recenter the
FIFO. If AUTO_FIFO_INIT is enabled, PHERR is con-
nected to PHINIT internally. Then, the FIFO is
centered automatically. PHERR will go inactive when
the realignment is complete or the drift has fallen to a
level within the specified maximum of 2 ps. (See
Figure 23, FIFO Initialization.)
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 5,
Transmitter Functional Block Diagram, is comprised of
staged registers and 2:1 multiplexers. The 16-bit wide
data output from the FIFO is presented to the first reg-
ister/2:1 multiplexer and converted from 16 bits to 8
bits wide. This procedure is repeated to convert to 4, 2
and finally 1-bit wide serial data.
Transmit Built-In Self Test Mode
The S19237 circuitry includes a PRBS generator and
a checker. The transmit built-in self test allows for the
verification of the serial data path, CRU, CSU and
most of the other blocks in the S19237. The S19237
goes in the transmit BIST mode when TX_BIST_EN is
programmed to logic high.
Once the S19237 is in the transmit BIST mode, the
PRBS generator will start sending the pattern through
the parallel input data path. The pattern can be a
PRBS pattern or a user defined pattern depending
upon the PRBS_SELECT[1:0] settings. See Table 11
for details. The user defined pattern can be loaded
through the BIST_PTRN[15:0] register. There are two
modes of transmit BIST operation:
1.
Normal operation with DLEB disabled
2.
Normal operation with DLEB enabled
When the diagnostic loopback mode is not active, the
serial output data (TSDP/N) must be looped back into
the serial input (SERDATIP/N) for the transmit PRBS
checker to work with the transmit PRBS generator. If
the diagnostic loopback mode is enabled, the TSDP/N
outputs will be internally looped back into the SER-
DATIP/N inputs.
Once the TX_BIST_EN input is programmed to logic
high, the transmit PRBS checker will be activated but
will not start checking for the valid data pattern until
RX_LOCKDET is active. This will ensure that valid
data is being passed through the receive channel.
Once the RX_LOCKDET is active, the checker will
begin its initialization phase for 15 CRU_REFCLK
cycles. The transmit checker reads the parallel data
output and figures out the next PRBS pattern in the ini-
tialization phase. After the checker is initialized, it will
compare the parallel data output with the calculated
pattern. If the parallel data output does not match the
calculated pattern, the TX_BIST_ERR flag will be set
active and the number of errors will start accumulating
on the BER_COUNT[9:0] register. The bit error rate
range can be selected with the appropriate setting of
the BER_SELECT[1:0]. See Table 12 for details of set-
ting the range for bit error rate.
The TX_BIST_ERR flag can be cleared by asserting
TX_BIST_CLR in the TX_BIST_EN mode or by reset-
ting (RSTB) the S19237. Once the TX_BIST_CLR
signal has been received by the checker, it will go back
to the initialization phase. TX_BIST_CLR is an active
相关PDF资料 |
PDF描述 |
|---|---|
| S1950E-FREQ-OUT25 | CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 125 MHz, ACMOS OUTPUT |
| S1F78100Y2A0 | 6 V FIXED POSITIVE REGULATOR, PSSO3 |
| S1F78100Y2B0 | 5 V FIXED POSITIVE REGULATOR, PSSO3 |
| S1F78100Y2C0 | 3.2 V FIXED POSITIVE REGULATOR, PSSO3 |
| S1F78100Y2F0 | 2.2 V FIXED POSITIVE REGULATOR, PSSO3 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
发布紧急采购，3分钟左右您将得到回复。