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S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
AMCC Confidential and Proprietary
DS1454
15
Data Sheet
The BOLD CELLS denote the default state
Post-Amp Equalization Adjust (PAEQUADJ[2:0]) –
(ISI Compensation Control) MDIO Register
The Post-Amp Equalization Adjust (PAEQUADJ[2:0])
(ISI Compensation Control) inputs may be used for
serial input data equalization adjustment control in
order to meet the 10 Gigabit Ethernet jitter tolerance
requirements. PAEQUADJ[2:0] controls the serial data
input equalization adjustment control. These control
inputs select the degree of compensation for losses
due to SMA connectors, skin-effect losses and dielec-
tric losses. This is not an adaptive type of equalization.
See Table
8 for details of the post-amp equalization
adjust settings. These inputs are only accessible
through the MDIO bus registers.
The BOLD CELLS denote the default state. See AN1464 Post Amp
Equalization Adjust Application Note.
PAOFFADJ[7:0] Settings for Offset Adjustment
7
6
5
4
3
2
1
0
α
SERDATIP-
SERDATIN =
1
0
254
126 *
mV
1
255
127 *
mV
Table 7. Adaptive Post-Amplifier Offset Adjust
ADAPOFFADJ
Adaptive Offset Adjust Control
0
Inactive. (PAOFFADJ[9:0] must be exter-
nally controlled for offset adjustment)
1
Active (Set the resolution through PAOF-
FADJ[9:8]. PAOFFADJ[7:0] are adap-
tively controlled to enhance BER)
Table 6. Post-Amplifier Offset Adjust (Continued)
Table 8. Post-Amplifier Equalization Adjust
PAEQUADJ Input - ISI Compensation Control
2
1
0
Equalization
(Input Eye Opening)
High Freq
AC Gain Boosting
(dB)
0
No Equalization
-0.8 dB
0
1
0% to 5%
1.4 dB
0
1
0
5% to 10%
2.4 dB
0
1
10% to 15%
3.9 dB
1
0
15% to 20%
4.4 dB
1
0
1
20% to 25%
4.4 dB
1
0
25% to 30%
5.9 dB
1
30% to 35%
7.5 dB