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参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 15/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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22
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
high level sensitive input. In order for the checker to
clear the TX_BIST_ERR flag, the TX_BIST_CLR must
be asserted high.
Also the BER_RSTB input register resets the
BER_OUT[9:0] after each terminal count. BER_RSTB
is a active high input. When active BER_OUT[9:0] is
not reset after each terminal count, but instead contin-
ues to accrue errors. When inactive, BER_OUT[9:0] is
reset to zero error value after each terminal count. The
TERM_COUNT output monitors for the terminal count
of the PRBS checker. The terminal count is set by the
BER_SELECT[1:0] register. See Table 12 for details.
Each transition of TERM_COUNT signal indicates that
the terminal count has been reached. This signal is ini-
tially set low upon RSTB or when TX_BIST_EN/
RX_BIST_EN are activated. The TERM_COUNT
makes a low to high transition when the first terminal
count is reached. A transition on TERM_COUNT will
set the BER_COUNT[9:0] register to zero depending
upon the BER_RSTB setting. When BER_RSTB is
active (high), BER_OUT[9:0] is not reset after each
terminal count, but instead continues to accrue errors.
The BER_OVERFLOW output will indicate if the
BER_COUNT[9:0] has overflowed. When t he
BER_OVERFLOW goes active, the bit error rate range
select (BER_SELECT[1:0]) needs to be changed. This
signal is active high and is latched high. This signal
mo nito rs the RX c hec ker co un t whe n the
RX_BIST_EN is active and TX checker count when
TX_BIST_EN is active.
RECEIVER FUNCTIONAL DESCRIPTION
The S19237 transceiver chip provides the first stage of the
digital processing of a receive SONET STS-192/10 Giga-
bit Ethernet bit-serial stream. It converts the 9.953 Gbps
bit-serial data stream into a 622.08 Mbps 16-bit parallel
data format (or equivalent FEC/10 Gigabit Ethernet rates).
Post-Amp
The S19237 limiting Post-Amp takes the differential
serial data from the SERDATIP/N pins and provides
36 dB small-signal gain. The input to the Post Amp
can be either AC or DC coupled. There is an offset
voltage adjustment (PAOFFADJ[9:0]) for DC coupling
in order to facilitate duty cycle distortion correction.
Clock Recovery
Clock recovery, as shown in the block diagram in
generates a clock that is the same frequency as the
incoming data bit rate at the serial data input. The
clock is phase aligned by a PLL so that it samples the
data in the center of the data eye pattern.
The Clock Recovery Unit (CRU) extracts a synchro-
no us sig nal from th e serial d ata inpu t u sin g a
frequency and Phase Lock Loop (PLL). The PLL
consists of a Voltage Controlled Oscillator (VCO),
Phase/Frequency Detectors (PFD), and a loop filter.
The frequency detector ensures predictable lock-up
conditions. It is used during acquisition and serves as
a means to pull the VCO into the range of the data rate
where the phase detector is capable of acquiring lock.
The phase detector used in the CRU is designed to
give minimum static phase error of the PLL. When a
transition has occurred, the value of the sample in the
vicinity of the transition indicates whether the VCO
clock leads or lags the incoming data, and the phase
detector produces a binary output accordingly.
When a loss of signal condition exists, the PLL locks
on to the rece iver ’ s inter nal r e fere nce clock
(CRU_REFCLK) to provide a steady output clock.
There are two pins (RXCAP1 and RXCAP2) to con-
nect the external capacitor and resistors in order to
adjust the PLL loop performance.
The phase relationship between the edge transitions
of the data and those of the generated clock are com-
pared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Con-
trolled Oscillator (VCO), wh ich g enerates th e
recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (CRU_REFCLK)
onto which the PLL locks when data is lost. If the fre-
quency of the incoming signal varies by a value
greater than that stated in Table 22, with respect to
CRU_REFCLKP/N, the PLL will be declared out of
lock, and the PLL will lock to the reference clock. The
assertion of LVCMOS Signal Detect (SDLVCMOS) will
also cause an out-of-lock condition.
The loop filter transfer function is optimized in order to
enable the PLL to track the jitter yet tolerate the minimum
transition density expected in a received SONET or 10
Gigabit Ethernet data signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
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