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参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 4/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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12
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
Phase Error (PHERR) – MDIO Register
Phase Error is an active high output. To prevent errors
caused by short set-up or hold times between the
PICLK and internally generated PCLK, the timing gen-
erator circuitry monitors the phase relationship
between the two clock domains. The Phase Error
(PHERR) signal will be asserted high at the start of the
PCLK cycle for which there may be setup/hold timing
violations between the PICLK and internal byte clock
(PCLK) timing domains. Since PHINIT will initialize the
FIFO if a high level is held for at least 50 ns, the FIFO
will be initialized if PHERR is connected to PHINIT on
the MDIO bus. This output is only accessible through
the MDIO bus register.
Phase Detector Output (PD_UP, PD_DWN) –
External Pin
These Phase Detector CML signals are the output of
an internal phase detector which may be used to
reduce jitter from an incoming CSU_REFCLK or from
an internally recovered clock used in loopback modes.
This output is typically used to drive an external loop
filter, which in turn controls a VCO that has its output
feeding the CSU_IN input. The internal phase detec-
tor, with the loop filter and VCO, form a PLL which may
be used to remove jitter from CSU_REFCLK or inter-
nal POCLK.
Transmit Built-In Self Test Error (TX_BIST_ERR) –
MDIO Register
Active h i gh t r an sm it b u ilt-in self test error
(TX_BIST_ERR) signal indicates a bit error in the
transmit built-in self test loop. After the transmit
checker is initialized, it will compare the parallel data
output with the calculated pattern. If the parallel data
output does not match the calculated pattern, the
TX_ B IST_ ERR flag will be se t active . The
TX_BIST_ERR flag can be cleared by asserting
TX_BIST_CLR in the TX_BIST_EN mode or by reset-
ting (RSTB) the S19237. The TX_BIST_ERR can also
be cleared with a rising edge of TX_BIST_EN. This
output is only accessible through the MDIO bus
register.
Transmit Alarm (TX_ALARM) – MDIO Register
The active high transmit alarm (TX_ALARM) signal
indicates an active alarm on the transmit output. This
output is an electrical “OR” of all the transmit alarms
[(“NOT” TX_LOCKDET) “OR” (PHERR)]. This output
is only accessible through the MDIO bus register.
RECEIVE INPUT PIN DESCRIPTION
Serial Data In (SERDATIP/N) – External Pin
The Serial Data In (SERDATIP/N) pins are the differ-
ential high Speed CML inputs. They receive inputs
from an optics module or other upstream logic device.
The S19237 extracts the clock from the SERDATIP/N
inputs and provides a recovered clock (internal
RSCLK) with re-timed parallel data. See Figure 27 for
the SERDATIP/N termination scheme. The SER-
DATIP/N is internally terminated with two 50
resistors in series. The two 50 resistors are center-
tapped with a 25 pF capacitor for use in single-ended
applications. The SERDATIP/N inputs must be AC
coupled. These pins are internally biased and termi-
nated 100 line-to-line.
SERDATIP/N Internal Termination (CENTER_TAP)
– External Pin
The SERDATIP/N is internally terminated with two 50
resistors in series. The two 50
resistors are center-
tapped with an internal 25 pF capacitor to Ground. The
input to the capacitor can be directly accessed through
the CENTER_TAP pin. This input should be connected
to an external broadband 0.01
F capacitor to ground if
driven single-ended or differential. This termination
scheme enables the S19237 to be driven in the single-
ended mode and offers better common mode noise
rejection. See Figure 27 for the SERDATIP/N termina-
tion scheme.
Receive Loop Filter (RXCAP1, RXCAP2) –
External Pin
The CRU external loop filter capacitor and resistors are
connected to the RXCAP1 and RXCAP2 pins. These
devices should be surrounded by a ground shield.
Component values should be as stated in Table 33,
Tr a n s m i t an d Rece ive Ext e rn al L o o p F ilt er
Components.
Lock-to-Reference (LCKREFN) – MDIO Register
The active low Lock-to-Reference (LCKREFN) input
register, when asserted low, will force the PLL to lock
to the local Reference Clock (CRU_REFCLK) and de-
assert RX_LOCKDET. The POCLKP/N will lock to the
CRU_REFCLKP/N in this mode. When the LCKREFN
is inactive (high), the POCLKP/N will lock to the valid
incoming serial data (SERDATIP/N). This input should
be programmed to logic high for normal operation.
This input is only accessible through the MDIO bus
register.
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相关代理商/技术参数 |
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| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
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