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参数资料
| 型号： | S19237PB13 |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | TRANSCEIVER, PBGA255 |
| 封装： | PLASTIC, BGA-255 |
| 文件页数： | 24/60页 |
| 文件大小： | 1418K |
| 代理商： | S19237PB13 |
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30
DS1454
AMCC Confidential and Proprietary
S19237 – SONET STS-192/10GbE CMOS Transceiver
with ISI Compensation
Data Sheet
TXCAP1
TXCAP2
Analog
D5
D6
Transmit Loop Filter Capacitors. Connections for external loop filter
capacitors and resistors. See Figure 22, External Loop Filter Compo-
ponents.
XVCO
MDIO
I
External Voltage Controlled Oscillator Select. This active high
input selects CSU_IN as the reference clock for the CSU block. In
this mode, CSU block uses CSU_IN as the reference clock instead of
using CSU_REFCLK directly. This signal can be accessed through
the MDIO bus register (Default = 0).
REFSEL
MDIO
I
Reference Select. Selects the reference clock frequency of the
transmit reference clock (CSU_REFCLK). See Table 1, Reference
can be accessed through the MDIO bus register (Default = 1).
PHINIT
MDIO
I
Phase Initialization. Asynchronous input that initializes the PHINIT.
See Figure 23, FIFO Initialization. This signal can be accessed
through the MDIO bus register (Default = 0).
AUTO_FIFO_INIT
MDIO
I
FIFO Initialization. This active high control input internally connects
the transmit FIFO signals (PHERR and PHINIT) and automatically
initializes the FIFO in case of a PCLK/PICLK set-up or hold time vio-
lation. This input can be accessed through the MDIO bus register
(Default = 1).
TX_BIST_EN
MDIO
I
Transmit Built-In Self Test Enable. This active high input enables
the transmit built-in self test mode. In this mode the PRBS generator
will start sending the pattern through the parallel inputs and transmit
checker will be activated. This signal can be accessed through the
MDIO bus register (Default = 0).
TX_BIST_CLR
MDIO
I
Transmit Built-In Self Test Clear. This active high level sensitive
input clears the transmit built-in self test error. The TX_BIST_ERR
flag can be cleared by asserting TX_BIST_CLR high in the BIST
mode or by resetting (RSTB) the S19237. This signal can be
accessed through the MDIO bus register (Default = 0).
CSU_INP
CSU_INN
REFCLK
Diff CML
I
B4
A4
Clock Synthesizer Input. Input to the internal CSU. Used to gener-
ate the serial transmit data. This input is internally biased and termi-
nated. This input must be AC coupled.
TXPD
MDIO
I
Transmitter Power Down. This active high control input powers
down the CSU and transmitter path. This signal can be accessed
through the MDIO bus register (Default = 0).
RECEIVER INPUTS
SERDATIP
SERDATIN
High
Speed
Diff CML
I
L1
N1
Serial Data Input. Differential high-frequency serial data input to lim-
iting post-amp for small signal gain. Internally biased and terminated
100
line-to-line (50 + 50 with center tap capacitor). This input
must be AC coupled.
CENTER_TAP
Analog
I
J1
Center Tap Input. This input should be connected to a broadband
0.01
F capacitor to ground.
Table 17. Input Pin Assignments and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S19237PB13-2 | 制造商:AppliedMicro 功能描述: |
| S19237PBICC | 制造商:AppliedMicro 功能描述:IC INTERFACE TRANSCEIVER LOW POWER CMOS 255 BGA 制造商:AMCC 功能描述: |
| S19238CBI | 制造商:AppliedMicro 功能描述: |
| S19250 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC |
| S19250PBIC | 制造商:AppliedMicro 功能描述:10G SERDES EDC/SFI-4 |
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