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参数资料
| 型号： | S29WS128J0PBFW002 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 |
| 封装： | 8 X 11.60 MM, LEAD FREE, FBGA-84 |
| 文件页数： | 49/97页 |
| 文件大小： | 2421K |
| 代理商： | S29WS128J0PBFW002 |
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May 11, 2006 S29WS-J_00_A6
S29WS128J/064J
53
D a ta
Sh eet
The following commands are not allowed when the Secured Silicon is accessible.
CFI
Unlock Bypass Entry
Unlock Bypass Program
Unlock Bypass Reset
Erase Suspend/Resume
Chip Erase
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-
ing two unlock write cycles, followed by the program set-up command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device automatically provides internally gen-
erated program pulses and verifies the programmed cell margin. Table 18, “Command
Definitions,” on page 60 shows the address and data requirements for the program command
sequence.
When the Embedded Program algorithm is complete, that bank then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 62
for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates the program operation. The program command se-
quence should be reinitiated once that bank has returned to the read mode, to ensure data
integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
grammed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or
cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding
read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to a array faster than using
the standard program command sequence. The unlock bypass command sequence is initiated by
first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass pro-
gram command sequence is all that is required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the pro-
gram address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting
in faster total programming time. The host system may also initiate the chip erase and sector
erase sequences in the unlock bypass mode. The erase command sequences are four cycles in
length instead of six cycles. Table 18, “Command Definitions,” on page 60 shows the require-
ments for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector
Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The
first cycle must contain the bank address and the data 90h. The second cycle need only contain
the data 00h. The array then returns to the read mode.
The device offers accelerated program operations through the ACC input. When the system as-
serts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may
then write the two-cycle Unlock Bypass program command sequence. The device uses the higher
voltage on the ACC input to accelerate the operation.
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PDF描述 |
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| S2M | 2 A, 1000 V, SILICON, RECTIFIER DIODE, DO-214AA |
| S2R72A44F12C4 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S29WS128J0PBFW01 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128J0PBFW10 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128J0PBFW11 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128N | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| S29WS128N0LBAI010 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
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