- 您现在的位置：买卖IC网 > PDF目录297338 > S29WS128J0PBFW002 (SPANSION LLC) 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 PDF资料下载
参数资料
| 型号： | S29WS128J0PBFW002 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 |
| 封装： | 8 X 11.60 MM, LEAD FREE, FBGA-84 |
| 文件页数： | 6/97页 |
| 文件大小： | 2421K |
| 代理商： | S29WS128J0PBFW002 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页
14
S29WS128J/064J
S29WS-J_00_A6 May 11, 2006
Dat a
S h ee t
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the inputs and control levels they require, and
the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care
Note: Default active edge of CLK is the rising edge.
Requirements for Asynchronous ReadOperation (Non-Burst)
To read data from the memory array, the system must first assert a valid address on Amax–
A0(A22-A0 for WS128J and A21-A0 for WS064J), while driving AVD# and CE# to VIL. WE# should
remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0.
Since the memory array is divided into four banks, each bank remains enabled for read access
until the command register contents are altered.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to
valid data at the output.
The internal state machine is set for reading array data in asynchronous mode upon device
power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-
tent occurs during the power transition.
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a pre-
set length. When the device first powers up, it is enabled for asynchronous read operation.
Operation
CE#
OE#
WE#
A22–0
DQ15–0
RESET#
CLK
AVD#
Asynchronous Read - Addresses Latched
L
H
Addr In
I/O
H
X
Asynchronous Read - Addresses Steady State
L
H
Addr In
I/O
H
X
L
Asynchronous Write
L
H
L
Addr In
I/O
H
X
L
Synchronous Write
L
H
L
Addr In
I/O
H
Standby (CE#)
HX
X
HIGH Z
H
X
Hardware Reset
XX
X
HIGH Z
L
X
Burst Read Operations
Load Starting Burst Address
L
X
H
Addr In
X
H
Advance Burst to next address with appropriate Data
presented on the Data Bus
LLH
HIGH Z
Burst
Data Out
HH
Terminate current Burst read cycle
HX
H
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
XX
H
HIGH Z
L
X
Terminate current Burst read cycle and start new
Burst read cycle
LX
H
HIGH Z
I/O
H
相关PDF资料 |
PDF描述 |
|---|---|
| S29WS128J0PBAW002 | 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 |
| S2M | 2 A, 1000 V, SILICON, RECTIFIER DIODE, DO-214AA |
| S2R72A44F12C4 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| S2V20-4000 | 1.7 A, 200 V, SILICON, RECTIFIER DIODE |
| S2V60-4070 | 1.7 A, SILICON, RECTIFIER DIODE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29WS128J0PBFW01 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128J0PBFW10 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128J0PBFW11 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128N | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| S29WS128N0LBAI010 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
发布紧急采购，3分钟左右您将得到回复。