参数资料
型号: S29WS128J0PBFW002
厂商: SPANSION LLC
元件分类: PROM
英文描述: 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84
封装: 8 X 11.60 MM, LEAD FREE, FBGA-84
文件页数: 73/97页
文件大小: 2421K
代理商: S29WS128J0PBFW002
May 11, 2006 S29WS-J_00_A6
S29WS128J/064J
75
D a ta
Sh eet
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle when wait state is set to less than 5 or
three additional clock cycle when wait state is set to 6 & 7 are inserted, clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 16. CLK Synchronous Burst Mode Read (Falling Active Clock)
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 17. Synchronous Burst Mode Read
Da
Da + 1
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tOEZ
tCEZ
tIACC
tACC
tBDH
4 cycles for initial access shown.
tRACC
Hi-Z
12
3
4
5
tRDYS
tBACC
tCR
Da
Da + 1
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
tCAS
tAAS
tAVC
tAVD
tAAH
tOE
tRACC
tOEZ
tCEZ
tIACC
tBDH
7 cycles for initial access shown.
Hi-Z
12
3
4
56
7
tRDYS
tBACC
tACC
tCR
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