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参数资料
| 型号： | S29WS128J0PBFW002 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 |
| 封装： | 8 X 11.60 MM, LEAD FREE, FBGA-84 |
| 文件页数： | 53/97页 |
| 文件大小： | 2421K |
| 代理商： | S29WS128J0PBFW002 |
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May 11, 2006 S29WS-J_00_A6
S29WS128J/064J
57
D a ta
Sh eet
Password Program Command
The Password Program Command permits programming the password that is used as part of the
hardware protection scheme. The actual password is 64-bits long. 4 Password Program com-
mands are required to program the password. The user must enter the unlock cycle, password
program command (38h) and the program address/data for each portion of the password when
programming. There are no provisions for entering the 2-cycle unlock cycle, the password pro-
gram command, and all the password data. There is no special addressing order required for
programming the password. Also, when the password is undergoing programming, Simultaneous
Operation is disabled. Read operations to any memory location will return the programming status
except DQ7. Once programming is complete, the user must issue a Read/Reset command to the
device to normal operation. Once the Password is written and verified, the Password Mode Locking
Bit must be set in order to prevent verification. The Password Program Command is only capable
of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-
out by the Embedded Program Algorithm with the cell remaining as a “0”. The password is all
F’s when shipped from the factory. All 64-bit password combinations are valid as a password.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only
when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is pro-
grammed and the user attempts to verify the Password, the device will always drive all F’s onto
the DQ data bus.
Also, the device will not operate in Simultaneous Operation when the Password Verify command
is executed. Only the password is returned regardless of the bank address. The lower two address
bits (A1–A0) are valid during the Password Verify. Writing the Secured Silicon Exit command re-
turns the device back to normal operation.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection
Mode Locking Bit, which prevents further verifies or updates to the password. Once programmed,
the Password Protection Mode Locking Bit cannot be erased and the Persistent Protection Mode
Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password
Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device requires a time out
period of approximately 150 s for programming the Password Protection Mode Locking Bit. Then
by writing “PL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then
the Password Protection Mode Locking Bit is programmed. If not, the system must repeat this
program sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection Mode Lock-
ing Bit Program command is accomplished by writing the Secured Silicon Sector Exit command
or Read/Reset command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent
Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever
being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the de-
vice is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set.
After issuing “SL/68h” at the fourth bus cycle, the device requires a time out period of approxi-
mately 150 s for programming the Persistent Protect ion Mode Locking Bit. Then by writ ing
“SMPL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the
Persistent Protection Mode Locking Bit is programmed. If not, the system must repeat this pro-
gram sequence from the fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking
Bit Program command is accomplished by writing the Secured Silicon Sector Exit command or
Read/Reset command.
相关PDF资料 |
PDF描述 |
|---|---|
| S29WS128J0PBAW002 | 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 |
| S2M | 2 A, 1000 V, SILICON, RECTIFIER DIODE, DO-214AA |
| S2R72A44F12C4 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| S2V20-4000 | 1.7 A, 200 V, SILICON, RECTIFIER DIODE |
| S2V60-4070 | 1.7 A, SILICON, RECTIFIER DIODE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29WS128J0PBFW01 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128J0PBFW10 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128J0PBFW11 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS128N | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| S29WS128N0LBAI010 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
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