参数资料
| 型号： | SC900841JVKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 116/192页 |
| 文件大小： | 0K |
| 描述： | IC POWER MGT 338-MAPBGA |
| 标准包装： | 2,000 |
| 应用： | PC，PDA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 338-TFBGA |
| 供应商设备封装： | 338-MAPBGA |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
LIGHTING SYSTEM
Table 73. Extended Backlight Control Registers Structure and Bits Description
TWOPTWO
7
Independent Zone (Backlight) Configuration Enable
x0 = Independent Zone Backlighting Option is disabled (Default)
x1 = Independent Zone Backlighting Option is Enabled
FSL4STRING (ADDR 0x1D4 - R/W - Default Value: 0x00)
BKLTBRTL2
7:0
LCD Backlight PWM Duty Cycle Settings for string 4 in single backlight configuration or for Strings 3-4 for independent
zone backlight configuration. See Table 70 for Duty Cycle Settings
FSLVBKLTADAPT (ADDR 0x1D5 - R/W - Default Value: 0x00)
S4ADAPT 0
Enable String 4 to be part of the adaptive boost control
x0 = Disable (Default)
x1 = Enable
Reserved
7:1
Reserved
CAMERA SCENE ILLUMINATION CURRENT
DRIVER
The 900841 supports one string of up to 5-6 LEDs for
Camera Scene Illumination. The string is powered from the
VBKLT boost regulator. The brightness control is done
through a 3-bit PWM duty cycle control with fixed PWM
frequency.
This string can also be used as an additional string for
backlight support, see VBKLT , in which case it is controlled
Camera Scene Illumination Drivers Status/Control
Registers and Bits Description
Table 74. Camera String Illumination Control Register Structure and Bits Description
Name
SLEDEN
SILTBRT
Reserved
Bits
0
3:1
7:4
Description
SSTRING (ADDR 0x2B - R/W - Default Value: 0x00)
Camera Scene Illumination Drivers Enable Bit
x0 = Disable
x1 = Enable
Camera Scene Illumination PWM Duty Cycle Settings
x0 = 12.5%
x4 = 62.5%
x1 = 25%
x5 = 75%
x2 = 37.5%
x6 = 87.5%
x3 = 50%
x7 = 100%
Reserved
SIGNALING/STATUS LED DRIVERS
The 900841 contains signaling/status LED drivers in the
form of two banks of RGB LED drivers. The signaling LED
drivers LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and
LEDB2 are independent current sink channels. Each driver
channel features programmable current levels via
LEDxBRT[1:0] as well as programmable PWM duty cycle
settings with LEDxDC[5:0]. By a combination of level and
PWM settings, each channel provides flexible LED intensity
control. By driving LEDs of different colors, color mixing can
be achieved. The default duty cycle, when a blink period is
set, not continuous, is 0.5 s on time.
Blue LEDs or bright green LEDs require more headroom
than red and normal green signal LEDs. In the application, a
5.0 V or equivalent supply rail is therefore required. This is
provided by the integrated 5.0 V boost converter VOTG.
Battery voltage can also be used to supply the RGB banks
directly via VPWR, if enough headroom is possible, by using
low forward voltage LEDs. Furthermore, each one of these
drivers can be supplied from a different source, as they are
completely independent. The PWM waveforms are
staggered from each other by one cycle of 32 kHz to
minimize sudden load changes on the LED supply.
The signaling LED drivers include ramp up and ramp down
patterns implemented in hardware. Ramp patterns for each
of the drivers are accessed with the corresponding
LEDxRAMP bit. The ramp itself is generated by increasing or
decreasing the PWM duty cycle with a 1/32 step every 1/64
seconds. The ramp time is therefore a function of the initial
set PWM cycle and the final PWM cycle. As an example,
starting from 0/32 and going to 32/32 will take 500 ms, while
going to from 8/32 to 16/32 takes 125 ms. Note that the ramp
function is executed upon every change in PWM cycle
900841
Analog Integrated Circuit Device Data
116
Freescale Semiconductor
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