参数资料
| 型号： | SC900841JVKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 56/192页 |
| 文件大小： | 0K |
| 描述： | IC POWER MGT 338-MAPBGA |
| 标准包装： | 2,000 |
| 应用： | PC，PDA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 338-TFBGA |
| 供应商设备封装： | 338-MAPBGA |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页
FUNCTIONAL DEVICE OPERATION
CLOCK GENERATION AND REAL TIME CLOCK (RTC)
the SET bit in Register B is clear. The SET bit in the “1” state
permits the program to initialize the time and calendar bytes
by stopping an existing update and preventing a new one
from occurring.
The primary function of the update cycle is to increment
the Seconds byte, check for overflow, increment the Minutes
byte when appropriate, and so forth, up through the month
and year bytes. The update cycle also compares each alarm
byte with the corresponding time byte and issues an alarm if
a match is present in all three positions.
Two methods of avoiding undefined output during updates
are usable by the program. In discussing the two methods, it
is assumed that at random points, user programs are able to
call a subroutine to obtain the time of day.
The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every update cycle, which
indicates that over 999 ms are available to read valid time
and date information. Before leaving the interrupt service
routine, the IRQF bit in Register C should be cleared.
The second method uses the update-in-progress bit (UIP)
in Register A, to determine if the update cycle is in progress.
The UIP bit will pulse once per second. Statistically, the UIP
bit will indicate that time and date information is unavailable
once every 3,640 attempts. After the UIP bit goes high, the
update cycle begins 244.1 μ s later. Therefore, if a low is read
on the UIP bit, the user has at least 244.1 μ s before the time/
calendar data will be changed. If a “1” is read in the UIP bit,
the time/calendar data may not be valid. The user should
avoid interrupt service routines which would cause the time
needed to read valid time/calendar data to exceed 244.1 μ s.
The RTC uses seven synchronous counters to increment
the time and calendar values. All seven timekeeping registers
are clocked by the same internal 1.0 Hz clock, so updates
occur simultaneously, even during rollover. After the counters
are incremented, the current time is compared to the time-of-
day alarm registers 30.5 μ s later, and if they match, the AF bit
in register C will be set.
The Update-cycle begins when the clock and calendar
registers are incremented, and ends when the alarm
comparison is complete. During this 30.5 μ s update cycle,
the time, calendar, and alarm bytes are fully accessible by the
processor program. If the processor reads these locations
during an update, the transitional output may be undefined.
The update in progress (UIP) status bit is set 244.1 μ s before
this interval, and is cleared when the update cycle completes.
interrupts. Writing a “1” to an interrupt-enable bit permits that
interrupt to be initiated when the event occurs. A “0” in the
interrupt-enable bit, prohibits the IRQF bit from being
asserted due to the interrupt cause.
If an interrupt flag is already set when the interrupt
becomes enabled, the IRQF bit is immediately activated,
though the interrupt initiating the event may have occurred
much earlier. Thus, there are cases where the program
should clear such earlier initiated interrupts before enabling
new interrupts.
When an interrupt event occurs, a flag bit is set to a “1” in
Register C. Each of the two interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
In the software scanned case, the program does not
enable the interrupt. The interrupt flag bit becomes a status
bit, which the software interrogates when it wishes. When the
software detects the flag is set, it is an indication to the
software an interrupt event occurred since the bit was last
read.
However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C, so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One or two flag bits may be found to be set
when Register C is used. The program should inspect all
utilized flag bits every time Register C is read to insure that
no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQF bit is
asserted high. IRQF is asserted as long as at least one of the
two interrupt sources has its flag and enable bits both set.
The processor program can determine that the RTC
initiated the interrupt by reading Register C. A “1” in bit 7
(IRQF bit) indicates that one or more interrupts have been
initiated by the part. The act of reading Register C clears all
the then active flag bits, plus the IRQF bit. When the program
finds IRQF set, it should look at each of the individual flag bits
in the same byte which have the corresponding interrupt
mask bits set and service each interrupt which is set. Again,
more than one interrupt flag bit may be set.
Interrupts
The RTC includes two separate, fully automatic sources of
interrupts to the processor. The alarm interrupt may be
programmed to occur at a rate of once per day. The update-
ended interrupt may be used to indicate to the program that
an update cycle is completed.
The processor program selects which interrupts, if any, it
ALARM INTERRUPT
The three alarm bytes may be used to generate a daily
alarm interrupt. When the program inserts an alarm time in
the appropriate hours, minutes, and seconds alarm locations,
the alarm interrupt is initiated at the specified time each day,
if the alarm enable bit is high.
wishes to receive. Two bits in Register B enable the two
900841
Analog Integrated Circuit Device Data
56
Freescale Semiconductor
相关PDF资料 |
PDF描述 |
|---|---|
| SC900AMLTRT | IC REG LDO ADJ .2A/.15A 20-MLPQ |
| SCCSP900842R2 | IC POWER MGT 36-WLCSP |
| SG1577ASY | IC REG CTRLR BST PWM VM 20-SOIC |
| SG1577DY | IC REG CTRLR BST PWM VM 20-DIP |
| SG3525ADW | IC REG CTRLR PWM VM 16-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SC900844JVK | 功能描述:PMIC 解决方案 PMUIC 5SW 14LDO 10BT ADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| SC900844JVKR2 | 功能描述:PMIC 解决方案 PMUIC 5SW 14LDO 10BT ADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| SC900A | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Programmable Penta ULDO with RESET and I2C Interface |
| SC900A100 | 制造商:Schneider Electric 功能描述:SUPERPROX ULTRASONIC PROXIMITY SENSOR 制造商:Schneider-Telemacanique 功能描述:SUPERPROX ULTRASONIC PROXIMITY SENSOR 制造商:SCHNEIDER ELECTRIC 功能描述:SUPERPROX ULTRASONIC PROXIMITY SENSOR |
| SC900A100FS | 制造商:Schneider Electric 功能描述:SUPERPROX ULTRASONIC PROXIMITY SENSOR 制造商:Schneider-Telemacanique 功能描述:SUPERPROX ULTRASONIC PROXIMITY SENSOR 制造商:SCHNEIDER ELECTRIC 功能描述:SUPERPROX ULTRASONIC PROXIMITY SENSOR |
发布紧急采购，3分钟左右您将得到回复。