参数资料
| 型号： | SC900841JVKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 53/192页 |
| 文件大小： | 0K |
| 描述： | IC POWER MGT 338-MAPBGA |
| 标准包装： | 2,000 |
| 应用： | PC，PDA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 338-TFBGA |
| 供应商设备封装： | 338-MAPBGA |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
CLOCK GENERATION AND REAL TIME CLOCK (RTC)
Table 22. PLL Control Register Structure and Bit
Description
TEST MODES
Test Mode Configuration
Name
Bits
Description
During evaluation and testing, the IC can be configured for
FSLPLLCNTL (ADDR 0x1E4 - R/W - Default Value: 0x1B)
PLLDIVIDE 2:0 PLL Divide Ratio and Effective VCO
Frequency Settings
x0 = 112, 3.670 MHz
x1 = 116, 3.801 MHz
x2 = 120, 3.932 MHz
x3 = 124, 4.063 MHz
x4 = 128, 4.194 MHz
x5 = 132, 4.325 MHz
x6 = 136, 4.456 MHz
x7 = 140, 4.588 MHz
normal operation or test mode via the ICTEST pin and other
register configurations. Details of Test mode programmability
are not documented herein, but should be referenced from
other Design for Test documentation.
Test modes are for Freescale use only, and must not be
accessed in applications. In test modes, signals are
multiplexed on existing functional pins. The ICTEST pin must
therefore be tied to ground (for normal operation) at the board
level, in product applications
Test mode also disables the thermal protection for high
temperature op life testing. A proprietary protocol is included
for scan chain test configurations, which reuses the SPI pins.
PLL16MEN
PLLEN
3
4
16 MHz frequency enable
x0 = 16 MHz clock disabled
x1 = 16 MHz clock enabled and PLL enabled
PLL Enable, even if there is no block
requesting a clock
x0 = PLL enabled based on device enables
only
In-package Trimming
During IC final test, several parameters are trimmed in the
package, such as the main bandgap, and other precision
analog functions. Trim registers are for Freescale use only
and must not be accessed in product applications. Fuse
programming circuitry will be blocked during normal and test
mode operation.
x1 = PLL enabled
Reserved
7:5
Reserved
CLOCK GENERATION AND REAL TIME CLOCK (RTC)
CLOCK GENERATION
A system clock is generated for internal digital circuitry, as
well as for external applications utilizing the clock output pins.
A crystal oscillator is used for the 32.768 kHz time base and
generation of related derivative clocks. If the crystal oscillator
is not running (for example, if the crystal is not present), an
internal 32 kHz oscillator will be used instead.
In addition, another crystal oscillator is used to generate a
26 MHz clock for Audio usage. This clock is also routed to the
companion chip, 900842, through the CLK26M pin.
Clocking Scheme
The internal 32 kHz oscillator is an integrated backup for
the crystal oscillator and provides a 32.768 kHz nominal
frequency at 50% accuracy, if running. The internal oscillator
only runs if a valid supply is available at the charger input,
battery, or coin cell, and would not be used as long as the
crystal oscillator is active. The crystal oscillator continues
running, supplied from one of the sources as described
previously, until all power is depleted or removed. All control
functions will run off the crystal derived frequency,
occasionally referred to as the "32 kHz".
At system startup, the 32 kHz clock is driven to the
CLK32K output pin, which is SPIVCC referenced. CLK32K is
provided as a peripheral clock reference. The driver is
M32KCLK bit is provided for direct SPI control. The
M32KCLK bit defaults to 0 to enable the driver and resets on
the RTCPORB to ensure the buffer is activated at the first
power up and configured as desired, for subsequent power
ups.
The drive strength of the output drivers is programmable
with CLK32KDRV[1:0] (master control bits that affect the
drive strength of CLK32K), see FSLOUTDRVCNTL2
If a switchover occurs between the two clock sources
(such as when the crystal oscillator is starting up), it will occur
during the active low phase of both clocks, to avoid clocking
glitches. A status bit, OSCSTP, is available to indicate to the
processor which clock is currently selected: OSCSTP=1
when the internal RC is used, and OSCSTP=0 if the XTAL
source is used.
The 26 MHz XTAL is necessary to provide a low jitter clock
operation for the Audio block of 900841. The 26 MHz signal
is needed internally for Audio operation, but is also provided
to the companion chip, 900842, via the CLK26M output pin
when the V33 voltage rail is enabled..
The drive strength of the output drivers is programmable
with CLK26MDRV[1:0] (master control bits that affect the
drive strength of CLK26M), see the FSLOUTDRVCNTL2
enabled by the startup sequencer. Additionally, a SPI bit
900841
Analog Integrated Circuit Device Data
Freescale Semiconductor
53
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