参数资料
| 型号： | SC900841JVKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 41/192页 |
| 文件大小： | 0K |
| 描述： | IC POWER MGT 338-MAPBGA |
| 标准包装： | 2,000 |
| 应用： | PC，PDA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 338-TFBGA |
| 供应商设备封装： | 338-MAPBGA |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
OVERVIEW
This section addresses the various interfaces and I/Os
Table 6. SPI Interface Pin Functionality
between the PMIC solution and the rest of the system.
System control interface includes the following:
? SPI interface: This is the serial communications interface
between the 900841and the System Control Unit (SCU) in
the platform controller hub.
? Communications (COMMs) Module Interface: This is the
interface between the various basic and advanced
communication modules, and the PMIC solution. It
Pin Name
SPICLK
MOSI
MISO
SPICSB
SPIVCC
SPI Functionality
SPI Clock Input (up to 25 MHz)
Master Out / Slave In (Serial Data In)
Master In / Slave Out (Serial Data Out)
Chip Select (Active Low)
SPI Bus Supply - 1.8 V typical
consists of two components:
? A Serial Communications port (Mini-SPI): This port
goes to the 900841 PMIC, which houses the digital core
supply of the COMMs module.
? Dedicated I/O signals for direct COMMs control of the
PMIC solution.
? Interrupt controller
? Sideband signals: These are I/O signals between the
900841 and the Ultra-mobile Platform architecture for
control and status reporting.
? I 2 S Bus Interface for Audio/Voice
? Freescale chip set communications signals: This includes
control and status reporting signal between the 900841
and the companion chip, 900842 in Freescale’s power
management solution.
? Special registers
SPI INTERFACE
The 900841 contains a SPI interface port, which allows a
host controller to access the register set. Using these
registers, 900841 resources can be controlled. The registers
provide information on the PMIC status, as well as
information on external signals.
The addressable register map spans 1024 registers of 8
data bits each. The map is not fully populated. A detailed
structure of the register set along with bit names, positions,
and basic descriptions, are given in Table 116 . Expanded bit
descriptions are included in the individual functional sections
for application guidance.
Note that not all bits are truly writable. Refer to the
individual sub-circuit descriptions and the Table 116 to
determine the read/write capability of each bit.
The Platform controller hub is the master, while the PMIC
is the slave. The SPI interface operates at a typical frequency
of 12.5 MHz, and at a maximum frequency of 25 MHz, with
lower speeds supported.
The SPI interface is configured in mode 1: clock polarity is
active high (CPOL = 0), and data is latched on the falling
edge of clock (CPHA = 1). The chip select signal, SPICSB,
is active low. The SPICSB line must remain active during the
entire SPI transfer. The MISO line will be tri-stated while
SPICSB is high.
The SPI frame consists of 24 bits: a Read/Write bit, a 10-
bit address code (MSB first), 5 "dead" bits and 8 data bits
(also MSB first). The Read/Write bit selects whether the SPI
transaction is a read or a write: for a write operation, the R/W
bit must be a one; for a read operation, it must be a zero.
For a read transaction, any data on the MOSI pin after the
address bits is ignored. The MISO pin will output the data
field pointed to by the 10-bit address loaded at the beginning
of the SPI sequence. SPI read backs of the address field and
unused bits are returned as zero. For read operations, the
PMIC supports address auto-increment.
For a write operation, once all the data bits are written, the
data is transferred into the registers on the falling edge of the
24th clock cycle. All unused SPI bits in each register must be
written to a zero.
To start a new SPI transfer, the SPICSB line must go
inactive and then active again. After the LSB of data is sent,
if the SPICSB line is held low, up to seven additional address/
data packets may be sent as writes to the PMIC. Refer to the
The following diagrams illustrate the SPI Write Protocol,
SPI Read Protocol, and SPI Timing.
Figure 5. SPI Read from PMIC Diagram (One Address/Data Packet shown)
900841
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
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