参数资料
| 型号： | SC900841JVKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 44/192页 |
| 文件大小： | 0K |
| 描述： | IC POWER MGT 338-MAPBGA |
| 标准包装： | 2,000 |
| 应用： | PC，PDA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 338-TFBGA |
| 供应商设备封装： | 338-MAPBGA |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
? When the 2nd level register is read, any 2nd level register
bits that were set at the point the SPI read strobe sweeps,
the register value into the SPI transmit shift register, that
bit will be cleared by the SPI self clear signal immediately
following the read strobe. This allows new interrupts to be
Table 10. Interrupt Registers Summary
recorded without being lost. If a new unmasked 2nd level
interrupt event happens just after the read of the 2nd level
register, the PMICINT pin will assert if the 1st level bit is
not masked.
Block
IRQ
Address
0x04
Register
Name
INTERRUP
RW
R
D7
EXT
D6
AUX
D5
VRFAUL
D4
GPIO
D3
RTC
D2
CHR
D1
ADC
D0
PWRBTN
Initial
0x00
T
T
IRQ
0x05
INTMASK
R/W
MEXT
MAUX
MVRFAU MGPIO
MRTC
MCHR
MADC
MPWRBT
0xFA
LT
N
RTC
POWER
0x1C
0x30
RTCC
VRFAULTI
R
R
IRQF
RSVD
PF (=0)
RSVD
AF
RSVD
UF
RSVD
RSVD
RSVD
RSVD
VRFAIL
RSVD
BATOCP
RSVD
THRM
0x00
0x00
NT
POWER
0x31
MVRFAUL
R/W
RSVD
RSVD
RSVD
RSVD
RSVD
MVRFAIL
MBATOC
MTHRM
0x03
TINT
P
ADC
0x5F
ADCINT
R
RSVD
RSVD
RSVD
RSVD
RSVD
OVERFLO
PENDET
RND
0x00
W
ADC
0x60
MADCINT
R/W
RSVD
RSVD
RSVD
RSVD
RSVD
MOVERFL MPENDET
MRND
0x00
OW
CHARGE
0xD0
CHRGINT
R
USBOV
DCLMT
BATDET
USBDE
COMP
TEMP
BATOVP
RSVD
0x00
R
P
T
CHARGE
R
0xD1
MCHRGIN
T
R/W MUSBO MDCLM MBATDE MUSBD MCOMP
VP
T
T
ET
MTEMP
MBATOVP
RSVD
0x00
GPIO
0xE8
GPIOINT
R
GPIINT7 GPIINT6 GPIINT5 GPIINT4 GPIINT3
GPIINT2
GPIINT1
GPIINT0
0x00
AUDIO
0X197
AUD24
R
RSVD
RSVD
RSVD
RSVD
HSDET
HPDET
SWMPINT SWLPINT
0X00
AUDIO
0X198
AUD25
RW
RSVD
RSVD
RSVD
RSVD
MHSDE
MHPDET
MSWMPI MSWLPIN 0X0F
T
NT
T
Notes
12. Because of the design of the clear on read logic, any interrupt event is allowed to happen at any time. If the interrupt event happens
close to when a read of the interrupt register happens, if the SPI read captures that interrupt bit as being set, then that bit will get cleared.
If the read does not capture the bit as being set, it will not be cleared. In this way no interrupt events are lost.
13. The 2nd level interrupts that get "Ored" together to set the 1st level interrupt bits can block other 2nd level interrupts from setting the 1st
level interrupt register. This is because if any of the 2nd level interrupts is high, the output of the OR will remain high, blocking the other
2nd level interrupt’s rising edge. This should not be a problem. because when the 2nd level register is read, the SCU will see all the bits
that are active when it is read. The software will decide which one to service first, just as it needs to do when more than one 1st level
interrupt bits are set when that register is read.
14. Masking has no affect on interrupt bits being set or cleared. Masking just prevents the interrupt event from asserting the interrupt pin. If
an interrupt bit is set, but is masked, the interrupt pin does not assert. If the mask bit is cleared while the bit is still set, the interrupt pin
will assert. Most interrupt registers have 1st and 2nd level mask bits. Both mask bits must be in the unmasked state to generate an
interrupt to the SCU.
15. Some 2nd level interrupt registers are level sensitive. If the level that sets these interrupts registers is active when the register is read,
it will clear during the active time of the clear on read signal and then reassert. This will reassert the 1st level interrupt bit.
16. The GPIO interrupts do not have interrupt masking bits, they have interrupt prevention bits. This is controlled by bits 5:4 of the GPIO
control register. See GPIOs for more details on using the GPIO as interrupt inputs.
17. Interrupts generated by external events are de-bounced. Therefore, the event needs to be stable throughout the de-bounce period
before an interrupt is generated. Nominal de-bounce periods for each event are documented in Table 11 . Due to the asynchronous
nature of the de-bounce timer, the effective de-bounce time can vary slightly.
900841
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
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