![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_107.png)
91
b. When an instruction that rewrites the PC in a delay slot is decoded
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L, @Rm+, SR
c. When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions
Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the
instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,
MD, and RB bits in SR are set to 1 and a branch occurs to PC
= VBR + H'0100. When an
undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.
User break point trap
Conditions: When a break condition set in the user break point controller is satisfied
Operations: When a post-execution break occurs, the PC of the instruction immediately
after the instruction that set the break point is set in the SPC. If a pre-execution break
occurs, the PC of the instruction that set the break point is set in the SPC. SR when the
break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC
= VBR + H'0100. See section 7, User Break Controller,
for more information.
4.5.3
Interrupts
1.
NMI
Conditions: NMI pin assert
Operations: The PC and SR after the instruction that receives the interrupt are saved to the
SPC and SSR, respectively. H'01C0 is set to INTEVT. The BL, MD, and RB bits of the SR
are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by
SR.IMASK and received with top priority when the SR’s BL bit is 0. When the BL bit is 1,
the interrupt is masked when BLMSK in ICRI is a logic zero and not masked when BLMSK
in ICRI is a logic one. See section 6, Interrupt Controller, for more information.
2.
IRL Interrupts
Conditions: The value of the interrupt mask bits in SR is lower than the IRL3–IRL0 level and
the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at
the time the interrupt is accepted is saved to SSR. The code corresponding to the
IRL3–IRL0 level is set in INTEVT. The corresponding code is given as H'200 +
B'(IRL3–IRL0)
× H'20. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to
VBR + H'0600. The received level is not set in SR.IMASK. See section 6, Interrupt
Controller, for more information.