![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_259.png)
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Area 6: Area 6 physical addresses A28–A26 are 110. Addresses A31–A29 are ignored and the
address range is the 64 Mbytes at H'18000000 + H'20000000
× n – H'1BFFFFFFF + H'20000000
× n (n = 0–6, n = 1–6 is the shadow space).
Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be
connected to this space. When the PCMCIA interface is used, the IC memory card interface
address range is the 32 Mbytes at H'18000000 + H'20000000
× n – H'19FFFFFFF + H'20000000 ×
n and the I/O card interface address range is the 32 Mbytes at H'1A000000 + H'20000000
× n –
H'1BFFFFFFF + H'20000000
× n (n = 0–6, n = 1–6 is the shadow space).
For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width
using the A6SZ1–A6SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be
selected as the bus width using the A6SZ1–A6SZ0 bits of BCR2.
When the area 6 space is accessed and ordinary memory is connected, a CS6 signal is asserted. An
RD signal that can be used as OE and the WE0–WE3 signals for write control are also asserted.
When the PCMCIA interface is used, the CE1 signal, CE2 signal, OE signal, and WE , IORD, and
IOWR signals are asserted.
The number of bus cycles is selected between 0 and 10 wait cycles using the A6W2–A6W0 bits of
WCR2. The bus cycle pitch of the burst cycle is determined within a range of 2–10 according to
the number of waits. When a PCMCIA interface is used, the setup and hold times of address
CE1B and CE2B for the read/write strobe signals can be set in the range 0.5–3.5 using A6TED1–
A6TED0 and A6TEH1–A6TEH0 bits of the PCR register.
10.3.3
Basic Interface
Basic Timing: The basic interface of the SH7709 uses strobe signal output in consideration of the
fact that mainly static RAM will be directly connected. Figure 10.6 shows the basic timing of
normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is
asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2
clock falling edge to secure the negation period. Therefore, in case of access at minimum pitch,
there is a half-cycle negation period.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only
the WE signal for the byte to be written is asserted. For details, see section 10.3.1, Endian/Access
Size and Data Alignment.
Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes
continuously. The bus is not released during this transfer. For cache misses that occur during byte
or word operand accesses or branching to odd word boundaries, the fill is always performed by