![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_192.png)
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As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by
4 by PLL circuit 2 before being supplied inside the SH7709, allowing a low crystal frequency to
be used. A crystal oscillation frequency of 5 MHz to 10 MHz can be used, and the CKIO
frequency range is 20 MHz to 40 MHz.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Mode 3: An external clock is input from the EXTAL pin and undergoes waveform shaping by
PLL circuit 2 before being supplied inside the SH7709. PLL circuit 1 is off in the default state at
power-on reset, and PLL circuit 1 can be selected as on or off, enabling power consumption to be
kept lower than in mode 0. An input clock frequency of 16 MHz to 25 MHz can be used, and the
CKIO frequency range is 16 MHz to 25 MHz.
Mode 4: The on-chip crystal oscillator operates, with its output supplied inside the SH7709 as a
square waveform by PLL circuit 2. PLL circuit 1 is off in the default state at power-on reset, and
PLL circuit 1 can be selected as on or off, enabling power consumption to be reduced accordingly.
A crystal oscillation frequency of 16 MHz to 25 MHz can be used, and the CKIO frequency range
is 16 MHz to 25 MHz.
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to the SH7709. In modes 0 to 4, the system clock is generated from
the output of the SH7709’s CKIO pin. Consequently, if a large number of ICs are operating on the
clock cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-
scale system. If a large number of ICs are operating on the clock cycle, a clock generator with a
number of low-skew clock outputs can be provided, so that the ICs can operate synchronously by
distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.