![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_176.png)
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Table 8.4
Register States in Standby Mode
Module
Registers Initialized
Registers Retaining Data
Interrupt controller
—
All registers
Break controller
—
All registers
Bus state controller
—
All registers
On-chip clock pulse generator
—
All registers
Timer unit
TSTR register
Registers other than TSTR
Realtime clock
—
All registers
The procedure for moving to standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT. Set the
WDT’s timer counter (WTCNT) and the CKS2–CKS0 bits of the WTCSR register to
appropriate values to secure the specified oscillation settling time.
2. When PLL circuit 1 is running in clock modes 3–6, clear the PSTBY and PLLEN bits in the
frequency control register (FRQCR) to 0 to stop PLL circuit 1.
3. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed.
4. Standby mode is entered and the clocks within the chip are halted. The STATUS1 pin output
goes low and the STATUS0 pin output goes high.
8.4.2
Canceling Standby Mode
Standby mode is canceled by an interrupt (NMI, IRL, or on-chip supporting module) or a reset.
Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI,
IRQ, IRL, PINT*
1, or on-chip peripheral module (except interval timer)*2 interrupt is detected,
after the elapse of the time set in the WDT's timer control/status register, clocks are supplied to the
entire LSI, standby mode is exited, and the STATUS1 and STATUS0 pins both go low. Interrupt
exception processing is then executed, and the code corresponding to the interrupt source is set in
INTEVT and INTEVT2. After the branch to the interrupt processing routine, clear the STBY bit
in the STBCR register. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT
will continue operating and standby mode*
3 will be entered again when the count reaches H'00.
This function prevents data corruption due to a rise in voltage when the power supply is unstable,
for instance. In standby mode, interrupts are accepted even if the BL bit in the SR register is 1,
and so, if necessary, SPC and SSR should be saved to the stack before executing the SLEEP
instruction.
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until standby mode is exited. A condition for exiting standby mode is that the interrupt
request level (IRQ, IRL, on-chip supporting module) must be higher than the interrupt mask level
set in bits I3—I0 in the SR register.