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6.2
Interrupt Sources
There are four types of interrupt sources: NMI, IRQ, PINT, and on-chip peripheral modules. Each
interrupt has priority levels (0–16) with 0 the lowest and 16 the highest. Priority level 0 masks an
interrupt.
6.2.1
NMI Interrupts
The NMI interrupt has the highest priority level of 16. When the BLMSK bit of the interrupt
control register (ICR1) is 1 or the BL bit of the status register (SR) is 0, NMI interrupts are
accepted when the MAI bit of the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or
standby mode, the interrupt is accepted regardless of the BL. The NMI edge select bit (NMIE) in
the interrupt control register0 (ICR0) is used to select either the rising or falling edge. When the
NMIE bit of the ICR0 register is changed, the NMI interrupt is not detected for 20 cycles after
changing the ICR.NMIE to avoid a false detection of the NMI interrupt. NMI interrupt exception
processing does not affect the interrupt mask level bits (I3–I0) in the status register (SR).
When the BLMSK bit of the ICR1 register is set to 1 and only NMI interrupts are accepted, the
SPC register and SSR register are updated by the NMI interrupt handler, making it impossible to
return to the original processing from exception handling initiated prior to the NMI. Use should
therefore be restricted to cases where return is not necessary.
It is possible to wake the chip up from the standby state with an NMI interrupt (except when the
MAI bit of the ICR1 register is set to 1).
6.2.2
IRQ Interrupt
IRQ interrupts are input by priority from pins IRQ0–IRQ5 with a level or an edge. The priority
level can be set by priority setting registers C–D (IPRC–IPRD) in a range from levels 0–15.
When edge-sensing is used for an IRQ interrupt, clear the corresponding bit in IRR0 to 0 by
software to clear the interrupt source.
When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the
pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask
after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
It is necessary for an edge input interruopt detection to input a pulse width more than 2 cycle
width by P clock basis.
The interrupt mask bits (I3–I0) of the status register (SR) are not affected by IRQ interrupt
processing.
Interrupts IRQ4–IRQ0 and port interrupts (PINT0/1) can wake the chip up from the standby state
when the relevant interrupt level is higher than I3–I0 in the SR register (but only when the RTC 32
kHz oscillator is used).