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Area 1: Area 1 physical addresses A28–A26 are 001. Addresses A31–A29 are ignored and the
address range is H'04000000 + H'20000000
× n – H'07FFFFFFF + H'20000000 × n (n = 0–6, n =
1–6 is the shadow space).
Area 1 is the area specifically for the internal peripheral modules. The external memories cannot
be connected.
Control registers of peripheral modules shown below are mapped to this area 1. Their addresses
are physical address, to which logical addresses can be mapped with the MMU enabled.
\DMAC, PORT, IrDA, SCIF, ADC, DAC, INTC(except INTEVT, IPRA, IPRB)
Those registers must not be cached.
Area 2: Area 2 physical addresses A28–A26 are 010. Addresses A31–A29 are ignored and the
address range is H'08000000 + H'20000000
× n – H'0BFFFFFFF + H'20000000 × n (n = 0–6, n =
1–6 is the shadow space).
Ordinary memories like SRAM and ROM, as well as DRAM and SDRAM, can be connected to
this space. Byte, word, or longword can be selected as the bus width using the A2SZ1–A2SZ0 bits
of BCR2 for ordinary memory. For SDRAM, set longword using the SZ bit of MCR. When
DRAM is connected to Area 2, the bus width is fixed at 16 bits.
When the area 2 space is accessed, a CS2 signal is asserted. When ordinary memories are
connected, an RD signal that can be used as OE and the WE0–WE3 signals for write control are
also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the
A12W1 to A12W0 bits of WCR2.
When SDRAM is connected, the RAS signal, CAS signal, RD/WR signal, and byte controls
DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of
RAS, CAS, data timing, and address multiplexing is set with MCR.
When DRAM is connected, the RAS signal, CAS signal, and RD/WR signal are all asserted and
addresses multiplexed. Control of RAS2, CAS, data timing, and address multiplexing is set with
DCR.
Area 3: Area 3 physical addresses A28–A26 are 011. Addresses A31–A29 are ignored and the
address range is H'0C000000 + H'20000000
× n – H'0FFFFFFFF + H'20000000 × n (n = 0–6, n =
1–6 is the shadow space).
Ordinary memories like SRAM and ROM, as well as DRAM, and SDRAM, can be connected to
this space. Byte, word or longword can be selected as the bus width using the A3SZ1–A3SZ0 bits
of BCR2 for ordinary memory. For DRAM, word or longword can be selected using the SZ bit of
MCR. When SDRAM is connected, set to longword using the MCR register’s SZ bit.
When area 3 space is accessed, CS3 is asserted.