![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_464.png)
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Simultaneous Multiple Receive Errors: Table 14.14 indicates the state of the SCSSR
status flags when multiple receive errors occur simultaneously. When an overrun error occurs,
the SCRSR contents cannot be transferred to the SCRDR, so receive data is lost.
Table 14.14 SCSSR Status Flags and Transfer of Receive Data
Receive Error Status
SCSSR Status Flags
RDRF
ORER
FER
PER
Receive Data
Transfer
SCRSR
→ SCRDR
Overrun error
1
0
X*1
Framing error
0
1
0
O*2
Parity error
0
1
O
Overrun error + framing error
1
0
X
Overrun error + parity error
1
0
1
X
Framing error + parity error
0
1
O
Overrun error + framing error + parity error 1
1
X
Notes: 1. Receive data is not transferred from SCRSR to SCRDR.
2. Receive data is transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin
directly when a framing error (FER) is detected. In the break state, the input from the RxD
pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the
break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be
set to 1 again.
Sending a Break Signal: The TxD pin input/output condition and level can be determined
by means of the SCP0DT bit of the port SC data register (SCPDR) and bits SCP0MD0 and
SCP0MD1 of the port SC control register (SCPCR). These bits can be used to send breaks.
To send a break during serial transmission, clear the SCP0DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of the current transmission status, and 0 is output from the
TxD pin.
TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the
stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting
of the TEND flag has been confirmed, the stop bit will be in the process of transmission and
will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least
0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag
setting is confirmed.
Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only):
When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start