491
Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data is transferred from transmit FIFO
data register (SCFTDR) to transmit shift register (SCTSR), the quantity of data in SCFTDR
becomes less than the number of transmission triggers specified by the TTRG1 and TTRG0 bits in
FIFO control register (SCFCR), and writing the transmit data to SCFTDR is enabled.
Bit 5: TDFE
Description
0
The quantity of transmit data written to SCFTDR is greater than the specified
number of transmission triggers.
TDFE is cleared to 0 when the data exceeding the specified number of
transmission triggers is written to SCFTDR, software reads TDFE after it has
been set to 1, then writes 0 in TDFE.
1
The quantity of transmit data in SCFTDR is less than the specified number of
transmission triggers.
TDFE is set to 1 at reset or at standby mode, or when the quantity of
transmission data in SCFTDR becomes less than the specified number of
transmission triggers as a result of transmission. *1
Note:
Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data which can be
written when TDFE is 1 is "16 minus the specified number of transmission triggers". If
attempted to write additional data, the data is ignored. The quantity of data in SCFTDR
is indicated by the upper 8 bits of SCFTDR.
Bit 4—Break Detection (BRK): Indicates that a break signal is detected in received data.
Bit 4: BRK
Description
0
No break signal is being received (initial value).
BRK is cleared to 0 when the chip is reset or enters standby mode, or software
reads BRK after it has been set to 1, then writes 0 in BRK.
1
The break signal is received.*1
BRK is set to 1 when data including a framing error is received and a framing
error occurs with space 0 in the subsequent received data.
Note:
When a break is detected, transfer of the received data (H'00) to SCFRDR stops after
detection. When the break ends and the receive signal becomes mark 1, the transfer of
the received data resumes. The received data of a frame in which a break signal is
detected is transferred to SCFRDR. After this, however, no received data is transferred
until a break ends with the received signal being mark 1 and the next data is received.
Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data
register (SCFRDR).