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vii
10.3.1 Endian/Access Size and Data Alignment ........................................................................ 239
10.3.2 Description of Areas ................................................................................................................... 244
10.3.3 Basic Interface .............................................................................................................................. 247
10.3.4 DRAM Interface ........................................................................................................................... 254
10.3.5 Synchronous DRAM Interface ............................................................................................... 272
10.3.6 Burst ROM Interface .................................................................................................................. 289
10.3.7 PCMCIA Interface....................................................................................................................... 292
10.3.8
Waits between Access Cycles............................................................................................. 304
10.3.9 Bus Arbitration .............................................................................................................................. 305
Section 11 Direct Memory Access Controller (DMAC)..................................................... 307
11.1
Overview........................................................................................................................................................... 307
11.1.1 Features ............................................................................................................................................ 307
11.1.2 Block Diagram .............................................................................................................................. 309
11.1.3 Pin Configuration ......................................................................................................................... 310
11.1.4 Register Configuration............................................................................................................... 311
11.2
Register Descriptions.................................................................................................................................. 312
11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3).................................................. 312
11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ....................................... 313
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ............................ 314
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........................................ 315
11.2.5 DMA Operation Register (DMAOR).................................................................................. 321
11.3
Operation .......................................................................................................................................................... 323
11.3.1 DMA Transfer Flow .................................................................................................................... 323
11.3.2 DMA Transfer Requests............................................................................................................ 325
11.3.3 Channel Priority............................................................................................................................ 326
11.3.4 DMA Transfer Types .................................................................................................................. 330
11.3.5 Number of Bus Cycle States and
DREQ Pin Sampling Timing............................ 338
11.3.6 Source Address Reload Function ......................................................................................... 344
11.3.7 DMA Transfer Ending Conditions ........................................................................................ 345
11.4
Compare Match Timer (CMT) .............................................................................................................. 347
11.4.1 Overview .......................................................................................................................................... 347
11.4.2 Register Descriptions ................................................................................................................. 348
11.4.3 Operation.......................................................................................................................................... 351
11.4.4 Compare Match ............................................................................................................................ 352
11.5
Examples of Use ........................................................................................................................................... 354
11.5.1 Example of DMA Transfer between On-Chip IRDA and External Memory .... 354
11.5.2 Example of DMA Transfer between AD0 and External Memory
(Address Reload on)................................................................................................................... 354